radeon/llvm: Add helper function for getting sub reg indices

diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp
index 7a8a58e7cfea4d92a495090017229d853fc72eab..12b46654bb772137c7230c1bc5e11ba567ca92f0 100644 (file)
--- a/src/gallium/drivers/radeon/R600InstrInfo.cpp
+++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp
@@ -50,16 +50,13 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                            unsigned DestReg, unsigned SrcReg,
                            bool KillSrc) const
 {
-
-  unsigned subRegMap[4] = {AMDGPU::sel_x, AMDGPU::sel_y,
-                           AMDGPU::sel_z, AMDGPU::sel_w};
-
   if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
       && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
     for (unsigned i = 0; i < 4; i++) {
+      unsigned SubRegIndex = RI.getSubRegFromChannel(i);
       BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
-              .addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define)
-              .addReg(RI.getSubReg(SrcReg, subRegMap[i]))
+              .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
+              .addReg(RI.getSubReg(SrcReg, SubRegIndex))
               .addReg(0) // PREDICATE_BIT
               .addReg(DestReg, RegState::Define | RegState::Implicit);
     }

diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.cpp b/src/gallium/drivers/radeon/R600RegisterInfo.cpp
index 94752410bfb3abe4e3c038ed5fdc79708a35714e..c2e40c7214a002f287251f6b4ba8f100b323433d 100644 (file)
--- a/src/gallium/drivers/radeon/R600RegisterInfo.cpp
+++ b/src/gallium/drivers/radeon/R600RegisterInfo.cpp
@@ -112,4 +112,16 @@ const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
   case MVT::i32: return AMDGPU::R600_TReg32RegisterClass;
   }
 }
+
+unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const
+{
+  switch (Channel) {
+    default: assert(!"Invalid channel index"); return 0;
+    case 0: return AMDGPU::sel_x;
+    case 1: return AMDGPU::sel_y;
+    case 2: return AMDGPU::sel_z;
+    case 3: return AMDGPU::sel_w;
+  }
+}
+
 #include "R600HwRegInfo.include"

diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.h b/src/gallium/drivers/radeon/R600RegisterInfo.h
index f45995d7d8bc3a676c1933f7c3af0f9bdad5819d..60f6d53b2d882809f034c59dbcd8a81712dd12a8 100644 (file)
--- a/src/gallium/drivers/radeon/R600RegisterInfo.h
+++ b/src/gallium/drivers/radeon/R600RegisterInfo.h
@@ -46,6 +46,10 @@ struct R600RegisterInfo : public AMDGPURegisterInfo
   /// type to use in the CFGStructurizer
   virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
 
+  /// getSubRegFromChannel - Return the sub reg enum value for the given
+  /// Channel (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x)
+  unsigned getSubRegFromChannel(unsigned Channel) const;
+
 private:
   /// getHWRegIndexGen - Generated function returns a register's encoding
   unsigned getHWRegIndexGen(unsigned reg) const;