add debug print statements to investigate FakePHY

add some more names on dfi.Interface instances, again to see what is
going on in gtkwave traces of SocTest nmigen simulation

diff --git a/gram/core/controller.py b/gram/core/controller.py
index 15aaaf744a17d986ef8af5ac0647a98f63dfed49..96938936f3dd43913238de28786bcf360791ab7c 100644 (file)
--- a/gram/core/controller.py
+++ b/gram/core/controller.py
@@ -64,7 +64,8 @@ class gramController(Elaboratable):
             bankbits=geom_settings.bankbits,
             nranks=phy_settings.nranks,
             databits=phy_settings.dfi_databits,
-            nphases=phy_settings.nphases)
+            nphases=phy_settings.nphases,
+            name="mem_dfi")
 
         self._clk_freq = clk_freq
 

diff --git a/gram/dfii.py b/gram/dfii.py
index 895e6541c6f67b680a3cb1e86385c666f29b9607..323ba975735b5bce2c5b2e6437831b16179acfe6 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -59,6 +59,7 @@ class PhaseInjector(Elaboratable):
 
 class DFIInjector(Elaboratable):
     def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
+        print ("nranks", nranks, "nphases", nphases)
         self._nranks = nranks
 
         self._inti = dfi.Interface(addressbits, bankbits,
@@ -84,6 +85,9 @@ class DFIInjector(Elaboratable):
         for n, phase in enumerate(self._phases):
             m.submodules['phase_%d' % n] = phase
 
+        for phase in self._inti.phases:
+            print ("phase", phase)
+
         with m.If(self._control.w_data[0]):
             m.d.comb += self.slave.connect(self.master)
         with m.Else():

diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py
index c2bdbbf2acc73c29df65d34b3ef35b3d449f6304..a436fee62321a22dddfc1f53743a0142af76804f 100644 (file)
--- a/gram/phy/dfi.py
+++ b/gram/phy/dfi.py
@@ -34,6 +34,9 @@ def phase_description(addressbits, bankbits, nranks, databits):
 class Interface:
     def __init__(self, addressbits, bankbits, nranks, databits, nphases=1,
                        name=None):
+        print ("DFI Interface", name, "addr", addressbits,
+                "bankbits", bankbits, "nranks", nranks, "data", databits,
+                "phases", nphases)
         self.phases = []
         for p in range(nphases):
             p = Record(phase_description(addressbits, bankbits,

diff --git a/gram/phy/fakephy.py b/gram/phy/fakephy.py
index d1c4885f52c6c05234c2ae763720fa9bac905bdc..3b134cd5ab07899d5d045196eacca7489da97469 100644 (file)
--- a/gram/phy/fakephy.py
+++ b/gram/phy/fakephy.py
@@ -22,8 +22,8 @@ SDRAM_VERBOSE_OFF = 0
 SDRAM_VERBOSE_STD = 1
 SDRAM_VERBOSE_DBG = 2
 
-def Display(*args):
-    return Signal().eq(0)
+#def Display(*args):
+#    return Signal().eq(0)
 
 def Assert(*args):
     return Signal().eq(0)
@@ -511,7 +511,8 @@ class FakePHY(Elaboratable):
             bankbits    = self.bankbits,
             nranks      = self.settings.nranks,
             databits    = self.settings.dfi_databits,
-            nphases     = self.settings.nphases
+            nphases     = self.settings.nphases,
+            name="phy"
         )
 
     def elaborate(self, platform):