gas/

2013-04-09  Jan Beulich <jbeulich@suse.com>

	* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
	if there was none specified for moves between scalar and core
	register.

gas/testsuite/
2013-04-09  Jan Beulich <jbeulich@suse.com>

	* gas/arm/neon-omit.s: Add tests for suffix less VMOV.
	* gas/arm/neon-omit.d: Update accordingly.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c9b1e31237fabe6d3a42a1a7885926d9b31e4bc5..48ac7e5f217aea1831aa8789114cf2e9f0b80409 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2013-04-09  Jan Beulich <jbeulich@suse.com>
+
+       * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
+       if there was none specified for moves between scalar and core
+       register.
+
 2013-04-09  Jan Beulich <jbeulich@suse.com>
 
        * gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 83f66dd206cd7009618c706bb6b2e181ca110ab7..9b8d8c13d305f0241599335f65e0397b29811a4c 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -15360,6 +15360,16 @@ do_neon_mov (void)
         unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
         unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
 
+       /* .<size> is optional here, defaulting to .32. */
+       if (inst.vectype.elems == 0
+           && inst.operands[0].vectype.type == NT_invtype
+           && inst.operands[1].vectype.type == NT_invtype)
+         {
+           inst.vectype.el[0].type = NT_untyped;
+           inst.vectype.el[0].size = 32;
+           inst.vectype.elems = 1;
+         }
+
         et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
         logsize = neon_logbits (et.size);
 
@@ -15409,6 +15419,16 @@ do_neon_mov (void)
         unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
         unsigned abcdebits = 0;
 
+       /* .<dt> is optional here, defaulting to .32. */
+       if (inst.vectype.elems == 0
+           && inst.operands[0].vectype.type == NT_invtype
+           && inst.operands[1].vectype.type == NT_invtype)
+         {
+           inst.vectype.el[0].type = NT_untyped;
+           inst.vectype.el[0].size = 32;
+           inst.vectype.elems = 1;
+         }
+
        et = neon_check_type (2, NS_NULL,
                              N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
         logsize = neon_logbits (et.size);

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 28d8530b35825f3ebd579748ebe0b912a91db03d..510927ff3abadebd1e5a4ba2ffec03730c392370 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-09  Jan Beulich <jbeulich@suse.com>
+
+       * gas/arm/neon-omit.s: Add tests for suffix less VMOV.
+       * gas/arm/neon-omit.d: Update accordingly.
+
 2013-04-09  Jan Beulich <jbeulich@suse.com>
 
        * gas/arm/neon-addressing-bad.s: Add test for further invalid VST

diff --git a/gas/testsuite/gas/arm/neon-omit.d b/gas/testsuite/gas/arm/neon-omit.d
index 3a1eeab2ac80f3910da63317d977e9bd6e5340af..540f453b1b18d77af44b700af4163065d7612d5e 100644 (file)
--- a/gas/testsuite/gas/arm/neon-omit.d
+++ b/gas/testsuite/gas/arm/neon-omit.d
@@ -93,4 +93,6 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3954556    vsli\.16        q2, q3, #5
 0[0-9a-f]+ <[^>]+> f3bff6b7    vqshlu\.s64     d15, d23, #63.*
 0[0-9a-f]+ <[^>]+> f2b25386    vext\.8 d5, d18, d6, #3
+0[0-9a-f]+ <[^>]+> ee000b10    vmov(\.32)?     d0\[0\], r0
+0[0-9a-f]+ <[^>]+> ee100b10    vmov(\.32)?     r0, d0\[0\]
 0[0-9a-f]+ <[^>]+> f3020d54    vmul\.f32       q0, q1, q2

diff --git a/gas/testsuite/gas/arm/neon-omit.s b/gas/testsuite/gas/arm/neon-omit.s
index 35490a5fbbd4973e961af741c04540af7a6d2ba4..54f18174a38217611815fdaadbce42ed3990c8e5 100644 (file)
--- a/gas/testsuite/gas/arm/neon-omit.s
+++ b/gas/testsuite/gas/arm/neon-omit.s
@@ -96,5 +96,10 @@
        vqshlu.s64 d15,d23,#63
        vext.8 d5,d18,d6,#3
 
+@ Also test VMOV with omitted suffix:
+
+       vmov d0[0], r0
+       vmov r0, d0[0]
+
 @ PR 11136 - this used to crash the assembler.
        vmul.f32   q0,q1,q2