Call finalize() after CRG creation

diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py
index dbb336a75ad698cc4cb498b7f1392512f8a2dc9e..4fc7855092ffe7636d7156e9529c22ecf8d191e4 100644 (file)
--- a/mibuild/altera_quartus.py
+++ b/mibuild/altera_quartus.py
@@ -74,7 +74,6 @@ quartus_sta {build_name}.qpf
 class AlteraQuartusPlatform(GenericPlatform):
        def build(self, fragment, build_dir="build", build_name="top",
                        quartus_path="/opt/Altera", run=True):
-               self.finalize(fragment)
                tools.mkdir_noerror(build_dir)
                os.chdir(build_dir)
 

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index 2feb70e4d80c6d06b46f97da739d558ee5a5e7dc..86c12651e6164e7cbd6c9ad9a83b887ab8a6a9e4 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -209,6 +209,8 @@ class GenericPlatform:
                                frag = fragment + crg.get_fragment()
                        else:
                                frag = fragment
+                       # finalize
+                       self.finalize(fragment)
                        # generate Verilog
                        src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
                                return_ns=True, create_clock_domains=False, **kwargs)

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 2ff3abec3c30740208aca8b677770e1bb3d36dcc..69306f5aeffbde940f3cc1eeb5317fba909ffff8 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -151,7 +151,6 @@ class XilinxISEPlatform(GenericPlatform):
 
        def build(self, fragment, build_dir="build", build_name="top",
                        ise_path="/opt/Xilinx", source=True, run=True):
-               self.finalize(fragment)
                tools.mkdir_noerror(build_dir)
                os.chdir(build_dir)