ARM: Restrict the shift amount from a register to 8 bits.

The shift amount when taken from a register is supposed to be truncated to an
8 bit value.

diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index f96416168ec97ad23681d2f38a81a252a9d3520b..daac4ed3cc3460f3f93af402580136f6adcdec5d 100644 (file)
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -96,7 +96,7 @@ let {{
     secondOpRe = re.compile("secondOp")
     immOp2 = "imm"
     regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
-    regRegOp2 = "shift_rm_rs(Op2, Shift, shiftType, CondCodes<29:>)"
+    regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
 
     def buildDataInst(mnem, code, flagType = "logic"):
         global header_output, decoder_output, exec_output