soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 7e8b78d7b95f6a687bdb681ce97e1bfda2fd6dfe..942e4b7da37c87de0d83bba23a9ca00ad98852a4 100644 (file)
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -140,7 +140,7 @@ class Timeout(Module):
 
         # # #
 
-        timer = WaitTimer(cycles)
+        timer = WaitTimer(int(cycles))
         self.submodules += timer
         self.comb += [
             timer.wait.eq(master.stb & master.cyc & ~master.ack),
@@ -153,7 +153,7 @@ class Timeout(Module):
 
 
 class InterconnectShared(Module):
-    def __init__(self, masters, slaves, register=False, timeout_cycles=2**16):
+    def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
         shared = Interface()
         self.submodules.arbiter = Arbiter(masters, shared)
         self.submodules.decoder = Decoder(shared, slaves, register)