arch-arm: Avoid creating an empty byteEnable vector

This behaviour will be forbidden in following patches.
Instead, create an all true vector.

JIRA: https://gem5.atlassian.net/browse/GEM5-196

Change-Id: I61d2852610281f2d7c7a669dcb4d2728be194f52
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23524
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa
index dd3d5827cfb29e1647d0462b11f8ef18d6d5e659..b36c1b2711d7cade9b6adcadc2c86fdaf69b117f 100644 (file)
--- a/src/arch/arm/isa/insts/sve_mem.isa
+++ b/src/arch/arm/isa/insts/sve_mem.isa
@@ -774,7 +774,7 @@ let {{
         EA = XBase + ((int64_t) imm * %(memacc_size)s)''' % {
             'memacc_size': 'eCount / 8' if isPred else 'eCount'}
         loadRdEnableCode = '''
-        auto rdEn = std::vector<bool>();
+        auto rdEn = std::vector<bool>(memAccessSize, true);
         '''
         if isPred:
             loadMemAccCode = '''