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diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index a33ec4f5f7c00314005b1fc1e7d182ac453d8fef..1458466fd8f0d514c48cc5565d8897349e66959e 100644 (file)
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -179,16 +179,16 @@ maddedu r22,r6,r0,r3
 Pseudo-code:
 
 ```
-if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then   # Check RA<RB, for divide-by-0
-    dividend[0:(XLEN*2)-1] <- (RA) || (RC)    # Combine RA/RC, zero extend
-    divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB) # Extend to 128-bit
-    result <- dividend / divisor                 # Division
-    modulo <- dividend % divisor                 # Modulo
-    RT <- result[XLEN:(XLEN*2)-1]                # Store result in RT
-    RS <- modulo[XLEN:(XLEN*2)-1]                # Modulo in RC, implicit
-else                                     # In case of error
-    RT <- [1]*XLEN                               # RT all 1's
-    RS <- [0]*XLEN                               # RS all 0's
+if ((RA) <u (RB)) & ((RB) != [0]*64) then  # Check RA<RB, for divide-by-0
+    dividend[0:127] <- (RA) || (RC)        # Combine RA/RC, zero extend
+    divisor[0:127] <- [0]*64 || (RB)       # Extend to 128-bit
+    result <- dividend / divisor           # Division
+    modulo <- dividend % divisor           # Modulo
+    RT <- result[64:127]                   # Store result in RT
+    RS <- modulo[64:127]                   # Modulo in RC, implicit
+else                                       # In case of error
+    RT <- [1]*64                           # RT all 1's
+    RS <- [0]*64                           # RS all 0's
 ```
 
 Special registers altered: