add AXI4 migen

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
index c2be1964892e50ba747d4d1773215e0fd98099a7..61beb10e399ddd5a68f06b7d03ab62be360b36da 100644 (file)
--- a/shakti/m_class/AXI.mdwn
+++ b/shakti/m_class/AXI.mdwn
@@ -4,4 +4,8 @@ See also [[wishbone]] Bus
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
 * <https://github.com/alexforencich/verilog-axis>
-* https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl
+* <https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl>
+
+# AXI4 in nmigen
+
+* <https://github.com/peteut/migen-axi>