radeonsi: add another requirement for PARTIAL_ES_WAVE

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index e211e9274a45c969ffcdbb740647696283d00439..e65379993f7c5ac4e2d35ea43bec6bfb5ecae383 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -576,6 +576,32 @@ static bool si_initialize_pipe_config(struct si_screen *sscreen)
        return true;
 }
 
+static bool si_init_gs_info(struct si_screen *sscreen)
+{
+       switch (sscreen->b.family) {
+       case CHIP_OLAND:
+       case CHIP_HAINAN:
+       case CHIP_KAVERI:
+       case CHIP_KABINI:
+       case CHIP_MULLINS:
+       case CHIP_ICELAND:
+       case CHIP_CARRIZO:
+               sscreen->gs_table_depth = 16;
+               return true;
+       case CHIP_TAHITI:
+       case CHIP_PITCAIRN:
+       case CHIP_VERDE:
+       case CHIP_BONAIRE:
+       case CHIP_HAWAII:
+       case CHIP_TONGA:
+       case CHIP_FIJI:
+               sscreen->gs_table_depth = 32;
+               return true;
+       default:
+               return false;
+       }
+}
+
 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 {
        struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
@@ -593,7 +619,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
        sscreen->b.b.resource_create = r600_resource_create_common;
 
        if (!r600_common_screen_init(&sscreen->b, ws) ||
-           !si_initialize_pipe_config(sscreen)) {
+           !si_initialize_pipe_config(sscreen) ||
+           !si_init_gs_info(sscreen)) {
                FREE(sscreen);
                return NULL;
        }

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 63057241f5ee9ba3f4486eab3feef1c601646128..53529779481edd001011c689769b4d617a0870ba 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -42,6 +42,7 @@
 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
 #define SI_NUM_SMOOTH_AA_SAMPLES 8
+#define SI_GS_PER_ES 128
 
 /* Instruction cache. */
 #define SI_CONTEXT_INV_ICACHE          (R600_CONTEXT_PRIVATE_FLAG << 0)
@@ -85,6 +86,7 @@ struct si_compute;
 
 struct si_screen {
        struct r600_common_screen       b;
+       unsigned                        gs_table_depth;
 };
 
 struct si_blend_color {

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index aef85579085b2232e574b02f8cfaf4ea069902f6..264ab1b3817188da8aa2d6d329d94990090b62d0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3264,7 +3264,7 @@ static void si_init_config(struct si_context *sctx)
        si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
 
        /* FIXME calculate these values somehow ??? */
-       si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
+       si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
        si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
        si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
 

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index e58e474e320390be42113d54450ff95312902217..822e2d5544161535a9e53f47442038117d8f2cff 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -311,6 +311,10 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
        if (ia_switch_on_eoi)
                partial_es_wave = true;
 
+       /* GS requirement. */
+       if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
+               partial_es_wave = true;
+
        /* Hw bug with single-primitive instances and SWITCH_ON_EOI
         * on multi-SE chips. */
        if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&