Small improvements in Verilog front-end docs

diff --git a/README b/README
index 08478d4ef597105fc323fae3c71b703a290ff275..50105ed2d0cb4d87ff423709d8bebe79b50771ae 100644 (file)
--- a/README
+++ b/README
@@ -308,6 +308,10 @@ Verilog Attributes and non-standard features
   for everything that comes after the {* ... *} statement. (Reset
   by adding an empty {* *} statement.)
 
+- In module parameter and port declarations, and cell port and parameter
+  lists, a trailing comma is ignored. This simplifies writing verilog code
+  generators a bit in some cases.
+
 - Modules can be declared with "module mod_name(...);" (with three dots
   instead of a list of module ports). With this syntax it is sufficient
   to simply declare a module port as 'input' or 'output' in the module
@@ -383,6 +387,7 @@ from SystemVerilog:
 - The keywords "always_comb", "always_ff" and "always_latch", "logic" and
   "bit" are supported.
 
+
 Building the documentation
 ==========================
 

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index f8ccda18102f487902ebab5483d27a637ffd7028..576f068b3f870087767eb34dc9cca1168f6de691 100644 (file)
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -159,6 +159,9 @@ struct VerilogFrontend : public Frontend {
                log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
                log("the syntax of the code, rather than to rely on read_verilog for that.\n");
                log("\n");
+               log("See the Yosys README file for a list of non-standard Verilog features\n");
+               log("supported by the Yosys Verilog front-end.\n");
+               log("\n");
        }
        virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
        {