pass
self.add_process(sync_process())
- def add_clock(self, period, domain="sync"):
+ def add_clock(self, period, phase=None, domain="sync"):
if self._fastest_clock == self._epsilon or period < self._fastest_clock:
self._fastest_clock = period
half_period = period / 2
+ if phase is None:
+ phase = half_period
clk = self._domains[domain].clk
def clk_process():
yield Passive()
- yield Delay(half_period)
+ yield Delay(phase)
while True:
yield clk.eq(1)
yield Delay(half_period)
with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
for domain, period in clocks.items():
- sim.add_clock(period / 1e9, domain)
+ sim.add_clock(period / 1e9, domain=domain)
for domain, process in generators.items():
- sim.add_sync_process(process, domain)
+ sim.add_sync_process(process, domain=domain)
sim.run()