sram: do not use MemoryPort

diff --git a/milkymist/sram/__init__.py b/milkymist/sram/__init__.py
index f1f744397e6c3516c03a942d99b05f296b73dd11..7f0cfcb6a6117f7d5db20b5a5c3087fbdce51d3d 100644 (file)
--- a/milkymist/sram/__init__.py
+++ b/milkymist/sram/__init__.py
@@ -7,14 +7,18 @@ class SRAM:
                self.depth = depth
        
        def get_fragment(self):
+               # memory
+               mem = Memory(32, self.depth)
+               port = mem.get_port(write_capable=True, we_granularity=8)
                # generate write enable signal
-               we = Signal(BV(4))
-               comb = [we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
+               comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
                        for i in range(4)]
-               # split address
-               nbits = bits_for(self.depth-1)
-               partial_adr = Signal(BV(nbits))
-               comb.append(partial_adr.eq(self.bus.adr[:nbits]))
+               # address and data
+               comb += [
+                       port.adr.eq(self.bus.adr[:len(port.adr)]),
+                       port.dat_w.eq(self.bus.dat_w),
+                       self.bus.dat_r.eq(port.dat_r)
+               ]
                # generate ack
                sync = [
                        self.bus.ack.eq(0),
@@ -22,6 +26,4 @@ class SRAM:
                                self.bus.ack.eq(1)
                        )
                ]
-               # memory
-               port = MemoryPort(partial_adr, self.bus.dat_r, we, self.bus.dat_w, we_granularity=8)
-               return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])
+               return Fragment(comb, sync, memories=[mem])