* doc/c-arm.texi: Likewise.
* doc/c-d10v.texi: Likewise.
* doc/c-i370.texi: Likewise.
* doc/c-i960.texi: Likewise.
* doc/c-ia64.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-ns32k.texi: Likewise.
* doc/c-pdp11.texi: Likewise.
* doc/c-pj.texi: Likewise.
* doc/c-sh64.texi: Likewise.
* doc/c-sparc.texi: Likewise.
* doc/c-tic54x.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-vax.texi: Likewise.
* doc/internals.texi: Likewise.
+2002-12-18 Kazu Hirata <kazu@cs.umass.edu>
+
+ * doc/c-alpha.texi: Fix typos.
+ * doc/c-arm.texi: Likewise.
+ * doc/c-d10v.texi: Likewise.
+ * doc/c-i370.texi: Likewise.
+ * doc/c-i960.texi: Likewise.
+ * doc/c-ia64.texi: Likewise.
+ * doc/c-mmix.texi: Likewise.
+ * doc/c-ns32k.texi: Likewise.
+ * doc/c-pdp11.texi: Likewise.
+ * doc/c-pj.texi: Likewise.
+ * doc/c-sh64.texi: Likewise.
+ * doc/c-sparc.texi: Likewise.
+ * doc/c-tic54x.texi: Likewise.
+ * doc/c-v850.texi: Likewise.
+ * doc/c-vax.texi: Likewise.
+ * doc/internals.texi: Likewise.
+
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
if @code{$at} is used by the programmer.
@item macro
-Enables the expasion of macro instructions. Note that variants of real
+Enables the expansion of macro instructions. Note that variants of real
instructions, such as @code{br label} vs @code{br $31,label} are
considered alternate forms and not macros.
This is the generic @var{.align} directive. For the ARM however if the
first argument is zero (ie no alignment is needed) the assembler will
behave as if the argument had been 2 (ie pad to the next four byte
-boundary). This is for compatability with ARM's own assembler.
+boundary). This is for compatibility with ARM's own assembler.
@cindex @code{req} directive, ARM
@item @var{name} .req @var{register name}
shifted right by 2. This is used in situations such as loading a register
with the address of a function (or any other code fragment). For example, if
you want to load a register with the location of the function @code{main} then
-jump to that function, you could do it as follws:
+jump to that function, you could do it as follows:
@smallexample
@group
ldi r2, main@@word
@samp{*} is the current location counter. Unlike @samp{.} it is always
relative to the last USING directive. Note that this means that
-expressions cannot use multiplication, as any occurence of @samp{*}
+expressions cannot use multiplication, as any occurrence of @samp{*}
will be interpreted as a location counter.
All labels are relative to the last USING. Thus, branches to a label
@cindex floating point, ESA/390 (@sc{ieee})
@cindex ESA/390 floating point (@sc{ieee})
The assembler generates only @sc{ieee} floating-point numbers. The older
-floiating point formats are not supported.
+floating point formats are not supported.
@node ESA/390 Directives
@cindex branch statistics table, i960
A table of every such @code{Label} is also generated, so that the
external postprocessor @code{gbr960} (supplied by Intel) can locate all
-the counters. This table is always labelled @samp{__BRANCH_TABLE__};
+the counters. This table is always labeled @samp{__BRANCH_TABLE__};
this is a local symbol to permit collecting statistics for many separate
object files. The table is word aligned, and begins with a two-word
header. The first word, initialized to 0, is used in maintaining linked
This option instructs the assembler to mark the resulting object file
as using the ``constant GP without function descriptor'' data model.
This model is like the ``constant GP'' model, except that it
-additionaly does away with function descriptors. What this means is
+additionally does away with function descriptors. What this means is
that the address of a function refers directly to the function's code
entry-point. Normally, such an address would refer to a function
descriptor, which contains both the code entry-point and the GP-value
The @code{mmixal} documentation (@pxref{mmixsite}) specifies that global
registers allocated with the @samp{GREG} directive (@pxref{MMIX-greg}) and
initialized to the same non-zero value, will refer to the same global
-register. This isn't strictly enforcable in @code{@value{AS}} since the
+register. This isn't strictly enforceable in @code{@value{AS}} since the
final addresses aren't known until link-time, but it will do an effort
unless the @samp{--no-merge-gregs} option is specified. (Register merging
isn't yet implemented in @code{@value{LD}}.)
@section Syntax
I don't know anything about the 32x32 syntax assembled by
-@code{@value{AS}}. Someone who undersands the processor (I've never seen
+@code{@value{AS}}. Someone who understands the processor (I've never seen
one) and the possible syntaxes should write this section.
@section Floating Point
The default is to generate position-independent code.
@end table
-@subsection Instruction Set Extention Options
+@subsection Instruction Set Extension Options
These options enables or disables the use of extensions over the base
line instruction set as introduced by the first PDP-11 CPU: the KA11.
@cindex -mcis
@cindex -mno-cis
@item -mcis | -mno-cis
-Enable (or disable) the use of the commersial instruction set, which
+Enable (or disable) the use of the commercial instruction set, which
consists of these instructions: @code{ADDNI}, @code{ADDN}, @code{ADDPI},
@code{ADDP}, @code{ASHNI}, @code{ASHN}, @code{ASHPI}, @code{ASHP},
@code{CMPCI}, @code{CMPC}, @code{CMPNI}, @code{CMPN}, @code{CMPPI},
@cindex -mno-kev11
@item -mfis | -mkev11
@itemx -mno-fis | -mno-kev11
-Enable (or diasble) the use of the KEV11 floating-point instructions:
+Enable (or disable) the use of the KEV11 floating-point instructions:
@code{FADD}, @code{FDIV}, @code{FMUL}, and @code{FSUB}.
@cindex -mfpp
@cindex PJ options
@cindex options, PJ
-@code{@value{AS}} has two addiitional command-line options for the picoJava
+@code{@value{AS}} has two additional command-line options for the picoJava
architecture.
@table @code
@item -ml
In that example, the first longword may or may not have the least
significant bit set depending on whether the label is an SHmedia label
or an SHcompact label. The second longword will be the actual address
-of the label, regardless of what type of lable it is.
+of the label, regardless of what type of label it is.
@node SH64 Directives
@section SH64 Machine Directives
This directive declares use of a global application or system register.
It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
the symbol name for that register. If symbol name is @code{#scratch},
-it is a scratch register, if it is @code{#ignore}, it just surpresses any
+it is a scratch register, if it is @code{#ignore}, it just suppresses any
errors about using undeclared global register, but does not emit any
information about it into the object file. This can be useful e.g. if you
save the register before use and restore it after.
@code{.field} and @code{.string} are also allowed; the size of
@code{.field} is one bit, and @code{.string} is considered to be one
word in size. Only element descriptors, structure/union tags,
-@code{.align} and conditioanl assembly directies are allowed within
+@code{.align} and conditional assembly directives are allowed within
@code{.struct}/@code{.endstruct}. @code{.align} aligns member offsets
to word boundaries only. @var{ssize}, if provided, will always be
assigned the size of the structure.
@cindex @code{usect} directive, C54X
@item [@var{symbol}] .usect "@var{section_name}", @var{size}, [,[@var{blocking_flag}] [,@var{alignment_flag}]]
-Reserve space for variables in a named, uninitialzed section (similar to
+Reserve space for variables in a named, uninitialized section (similar to
.bss). @code{.usect} allows definitions sections independent of .bss.
@var{symbol} points to the first location reserved by this allocation.
The symbol may be used as a variable name. @var{size} is the allocated
number of parameters defined, the last parameter is assigned the string
equivalent of all remaining arguments. If fewer arguments are given
than parameters, the missing parameters are assigned empty strings. To
-include a comma in an argument, you must enclose the agument in quotes.
+include a comma in an argument, you must enclose the argument in quotes.
@cindex subsym builtins, C54X
@cindex C54X subsym builtins
The following symbols are recognized as memory-mapped registers:
@table @code
-@end table
\ No newline at end of file
+@end table
@samp{movea lo(here), r6, r6}
The reason for this special behaviour is that movea performs a sign
-extention on its immediate operand. So for example if the address of
+extension on its immediate operand. So for example if the address of
'here' was 0xFFFFFFFF then without the special behaviour of the hi()
pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
movea instruction would takes its immediate operand, 0xFFFF, sign extend
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
-@c VAX/VMS description exhanced and corrected by Klaus K"aempf, kkaempf@progis.de
+@c VAX/VMS description enhanced and corrected by Klaus K"aempf, kkaempf@progis.de
@ifset GENERIC
@node Vax-Dependent
@chapter VAX Dependent Features
preprocessor so that whitespace around colons is preserved. This is useful
when colons might be removed from the input after preprocessing but before
assembling, so that adjoining tokens can still be distinguished if there is
-whitespace, or concatentated if there is not.
+whitespace, or concatenated if there is not.
@item tc_frob_section
@cindex tc_frob_section
@item tc_frob_symbol
@cindex tc_frob_symbol
If you define this macro, GAS will call it for each symbol. You can indicate
-that the symbol should not be included in the object file by definining this
+that the symbol should not be included in the object file by defining this
macro to set its second argument to a non-zero value.
@item tc_frob_file
@item obj_sec_sym_ok_for_reloc
@cindex obj_sec_sym_ok_for_reloc
You may define this macro to indicate that it is OK to use a section symbol in
-a relocateion entry. If it is not, GAS will define a new symbol at the start
+a relocation entry. If it is not, GAS will define a new symbol at the start
of a section.
@item EMIT_SECTION_SYMBOLS
@item obj_frob_symbol
@cindex obj_frob_symbol
If you define this macro, GAS will call it for each symbol. You can indicate
-that the symbol should not be included in the object file by definining this
+that the symbol should not be included in the object file by defining this
macro to set its second argument to a non-zero value.
@item obj_frob_file
The @code{fr_subtype} field of a frag is an index into a CPU-specific
relaxation table. That table entry indicates the range of values that can be
stored, the number of bytes that will have to be added to the frag to
-accomodate the addressing mode, and the index of the next entry to examine if
+accommodate the addressing mode, and the index of the next entry to examine if
the value to be stored is outside the range accessible by the current
addressing mode. The @code{fr_symbol} field of the frag indicates what symbol
is to be accessed; the @code{fr_offset} field is added in.
If you generate frags separately for the basic insn opcode and any relaxable
operands, do not call @code{fix_new} thinking you can emit fixups for the
-opcode field from the relaxable frag. It is not garanteed to be the same frag.
+opcode field from the relaxable frag. It is not guaranteed to be the same frag.
If you need to emit fixups for the opcode field from inspection of the
relaxable frag, then you need to generate a common frag for both the basic
opcode and relaxable fields, or you need to provide the frag for the opcode to
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