Add dram core as submodule

diff --git a/examples/ecpix5.py b/examples/ecpix5.py
index ddc8bf37a74f52ed56c61e1960de6952e3aa11aa..7bf866b7b893e88eea1e053e8af8c21901b4d2d7 100644 (file)
--- a/examples/ecpix5.py
+++ b/examples/ecpix5.py
@@ -165,6 +165,7 @@ class DDR3SoC(CPUSoC, Elaboratable):
                m.submodules.timer   = self.timer
                m.submodules.intc    = self.intc
                m.submodules.ddrphy  = self.ddrphy
+               m.submodules.dramcore = self.dramcore
 
                m.submodules.sysclk = SysClocker()