sv: rd, rs1/2/3 become virtual so that sv_insn_t can override them

diff --git a/riscv/decode.h b/riscv/decode.h
index f9e3b6f649fec534693b25b48cdf20d201dcd085..7c2b89ec609da45a97818d5490802227fdb6bf46 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -76,10 +76,10 @@ public:
   int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
   int64_t u_imm() { return int64_t(b) >> 12 << 12; }
   int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
-  uint64_t rd() { return x(7, 5); }
-  uint64_t rs1() { return x(15, 5); }
-  uint64_t rs2() { return x(20, 5); }
-  uint64_t rs3() { return x(27, 5); }
+  uint64_t virtual rd() { return x(7, 5); }
+  uint64_t virtual rs1() { return x(15, 5); }
+  uint64_t virtual rs2() { return x(20, 5); }
+  uint64_t virtual rs3() { return x(27, 5); }
   uint64_t rm() { return x(12, 3); }
   uint64_t csr() { return x(20, 12); }