if (cell->type == "$alu" && port_name == "\\B")
return cell->getPort("\\BI");
- else if (cell->type == "$sub" && port_name == "\\B")
+ else if (cell->type == "$sub" && port_name == "\\B")
return RTLIL::Const(1, 1);
return RTLIL::Const(0, 1);
auto op = p.op;
RTLIL::IdString muxed_port_name = "\\A";
- if (op->getPort("\\A") == operand.sig) {
+ if (decode_port(op, "\\A", &assign_map) == operand)
muxed_port_name = "\\B";
- }
auto operand = decode_port(op, muxed_port_name, &assign_map);
- if (operand.sig.size() > max_width) {
+ if (operand.sig.size() > max_width)
max_width = operand.sig.size();
- }
muxed_operands.push_back(operand);
}
max_width = shared_op->getParam("\\Y_WIDTH").as_int();
- for (auto &operand : muxed_operands) {
+ for (auto &operand : muxed_operands)
operand.sig.extend_u0(max_width, operand.is_signed);
- }
-
for (const auto& p : ports) {
auto op = p.op;
module->remove(op);
}
- for (auto &muxed_op : muxed_operands) {
- if (muxed_op.sign != muxed_operands[0].sign) {
+ for (auto &muxed_op : muxed_operands)
+ if (muxed_op.sign != muxed_operands[0].sign)
muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed));
- }
- }
+
RTLIL::SigSpec mux_y = mux->getPort("\\Y");
RTLIL::SigSpec mux_a = mux->getPort("\\A");
shared_op->setParam("\\Y_WIDTH", conn_width);
- if (shared_op->getPort("\\A") == operand.sig) {
+ if (decode_port(shared_op, "\\A", &assign_map) == operand) {
shared_op->setPort("\\B", mux_to_oper);
shared_op->setParam("\\B_WIDTH", max_width);
} else {
auto op = p->op;
RTLIL::IdString muxed_port_name = "\\A";
- if (op->getPort("\\A") == shared_operand.sig) {
+ if (decode_port(op, "\\A", &assign_map) == shared_operand) {
muxed_port_name = "\\B";
}
log("\n");
log("This pass identifies mutually exclusive cells of the same type that:\n");
- log(" (a) share an input signal\n");
- log(" (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell allowing\n");
- log(" the cell to be merged and the multiplexer to be moved from\n");
- log(" multiplexing its output to multiplexing the non-shared input signals.\n");
+ log(" (a) share an input signal,\n");
+ log(" (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell,\n");
+ log("\n");
+ log("allowing the cell to be merged and the multiplexer to be moved from\n");
+ log("multiplexing its output to multiplexing the non-shared input signals.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE