CHANGES: update.

diff --git a/CHANGES b/CHANGES
index ed4399a74681255619dae74a040613465eff2169..836fead16a5851756323be19f78abe660beec87f 100644 (file)
--- a/CHANGES
+++ b/CHANGES
@@ -27,6 +27,7 @@
        - Revert to a single crt0 (avoid ctr/xip variants).
        - Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
        - Add AXI-Lite bus standard support.
+       - Add VexRiscv SMP CPU support.
 
        [> API changes/Deprecation
        --------------------------