[AARCH64]Fix TLS local exec model addressing code generation inconsistency.

gcc/

	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Correct
	the comment.
	* config/aarch64/aarch64.md * (tlsle_small_<mode>): Add left shift
	12-bit for higher part.

From-SVN: r220116

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a5676178d76bdcbaabb179bf6404cd75919fbcd0..57fb5f15dc8781a7c8ddb85725bc51c90e6c2937 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-01-26  Renlin Li  <renlin.li@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Correct
+       the comment.
+       * config/aarch64/aarch64.md (tlsle_small_<mode>): Add left shift 12-bit
+       for higher part.
+
 2015-01-26  Richard Biener  <rguenther@suse.de>
 
        PR middle-end/64764

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index dd49fcd89d8a9bde27446a84ae4668a3a84ed080..b923fdb08a8e653570e51cf516dc551955961704 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -818,8 +818,8 @@ tls_symbolic_operand_type (rtx addr)
 
    Local Exec:
    mrs  tp, tpidr_el0
-   add  t0, tp, #:tprel_hi12:imm
-   add  t0, #:tprel_lo12_nc:imm
+   add  t0, tp, #:tprel_hi12:imm, lsl #12
+   add  t0, t0, #:tprel_lo12_nc:imm
 */
 
 static void

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index bc49fbe68a978b3ca069c6d084f542773df84bcb..b81ecb273ae378004641adb58fe1f6bd884c83f8 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4224,7 +4224,7 @@
                    (match_operand 2 "aarch64_tls_le_symref" "S")]
                   UNSPEC_GOTSMALLTLS))]
   ""
-  "add\\t%<w>0, %<w>1, #%G2\;add\\t%<w>0, %<w>0, #%L2"
+  "add\\t%<w>0, %<w>1, #%G2, lsl #12\;add\\t%<w>0, %<w>0, #%L2"
   [(set_attr "type" "alu_sreg")
    (set_attr "length" "8")]
 )