+2011-06-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ * config/i386/crtfastmath.c [!__x86_64__ && __sun__ && __svr4__]:
+ Include <signal.h>, <ucontext.h>.
+ (sigill_caught): Define.
+ (sigill_hdlr): New function.
+ (set_fast_math) [!__x86_64__ && __sun__ && __svr4__]: Check if SSE
+ insns can be executed.
+ * config/sol2.h (ENDFILE_SPEC): Use crtfastmath.o if -ffast-math
+ etc.
+ * config/sparc/sol2.h (ENDFILE_SPEC): Remove.
+
2011-06-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/t-slibgcc-darwin: Move to ...
/*
- * Copyright (C) 2005, 2007, 2009 Free Software Foundation, Inc.
+ * Copyright (C) 2005, 2007, 2009, 2011 Free Software Foundation, Inc.
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
#include "cpuid.h"
#endif
+#if !defined __x86_64 && defined __sun__ && defined __svr4__
+#include <signal.h>
+#include <ucontext.h>
+
+static volatile sig_atomic_t sigill_caught;
+
+static void
+sigill_hdlr (int sig __attribute((unused)),
+ siginfo_t *sip __attribute__((unused)),
+ ucontext_t *ucp)
+{
+ sigill_caught = 1;
+ /* Set PC to the instruction after the faulting one to skip over it,
+ otherwise we enter an infinite loop. 4 is the size of the stmxcsr
+ instruction. */
+ ucp->uc_mcontext.gregs[EIP] += 4;
+ setcontext (ucp);
+}
+#endif
+
static void __attribute__((constructor))
#ifndef __x86_64__
/* The i386 ABI only requires 4-byte stack alignment, so this is necessary
if (edx & bit_SSE)
{
- unsigned int mxcsr = __builtin_ia32_stmxcsr ();
+ unsigned int mxcsr;
- mxcsr |= MXCSR_FTZ;
+#if defined __sun__ && defined __svr4__
+ /* Solaris 2 before Solaris 9 4/04 cannot execute SSE instructions even
+ if the CPU supports them. Programs receive SIGILL instead, so check
+ for that at runtime. */
+ struct sigaction act, oact;
+
+ act.sa_handler = sigill_hdlr;
+ sigemptyset (&act.sa_mask);
+ /* Need to set SA_SIGINFO so a ucontext_t * is passed to the handler. */
+ act.sa_flags = SA_SIGINFO;
+ sigaction (SIGILL, &act, &oact);
+
+ /* We need a single SSE instruction here so the handler can safely skip
+ over it. */
+ __asm__ volatile ("movss %xmm2,%xmm1");
+
+ sigaction (SIGILL, &oact, NULL);
+
+ if (sigill_caught)
+ return;
+#endif /* __sun__ && __svr4__ */
+
+ mxcsr = __builtin_ia32_stmxcsr () | MXCSR_FTZ;
if (edx & bit_FXSAVE)
{