Change avxvnni disassembler output from {vex3} to {vex}

gas/

	* testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from
	{vex3} to {vex}
	* testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.

opcodes/

	* i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 011b1b8003ba74d0bbb737751c009d62bc3541ec..762bc7cbfc583805b347ddfaeafbbee5becc6c5a 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2020-10-26  Lili Cui  <lili.cui@intel.com>
+
+       * testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from
+       {vex3} to {vex}
+       * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
+
 2020-10-21  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 
        PR target/26763

diff --git a/gas/testsuite/gas/i386/avx-vnni.d b/gas/testsuite/gas/i386/avx-vnni.d
index 6e31528cf222f0e05883631cfa520fafa6f94829..7d20c809730380b24b2ad8866833eaf1306fe971 100644 (file)
--- a/gas/testsuite/gas/i386/avx-vnni.d
+++ b/gas/testsuite/gas/i386/avx-vnni.d
@@ -9,27 +9,27 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:   62 f2 5d 08 50 d2       vpdpbusd %xmm2,%xmm4,%xmm2
  +[a-f0-9]+:   62 f2 5d 08 50 d2       vpdpbusd %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 50 d2          \{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 50 d2          \{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 50 11          \{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 50 11          \{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 50 d2          \{vex\} vpdpbusd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 50 d2          \{vex\} vpdpbusd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 50 11          \{vex\} vpdpbusd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 50 11          \{vex\} vpdpbusd \(%ecx\),%xmm4,%xmm2
  +[a-f0-9]+:   62 f2 5d 08 52 d2       vpdpwssd %xmm2,%xmm4,%xmm2
  +[a-f0-9]+:   62 f2 5d 08 52 d2       vpdpwssd %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 52 d2          \{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 52 d2          \{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 52 11          \{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 52 11          \{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 52 d2          \{vex\} vpdpwssd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 52 d2          \{vex\} vpdpwssd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 52 11          \{vex\} vpdpwssd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 52 11          \{vex\} vpdpwssd \(%ecx\),%xmm4,%xmm2
  +[a-f0-9]+:   62 f2 5d 08 51 d2       vpdpbusds %xmm2,%xmm4,%xmm2
  +[a-f0-9]+:   62 f2 5d 08 51 d2       vpdpbusds %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 51 d2          \{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 51 d2          \{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 51 11          \{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 51 11          \{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 51 d2          \{vex\} vpdpbusds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 51 d2          \{vex\} vpdpbusds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 51 11          \{vex\} vpdpbusds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 51 11          \{vex\} vpdpbusds \(%ecx\),%xmm4,%xmm2
  +[a-f0-9]+:   62 f2 5d 08 53 d2       vpdpwssds %xmm2,%xmm4,%xmm2
  +[a-f0-9]+:   62 f2 5d 08 53 d2       vpdpwssds %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 53 d2          \{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 53 d2          \{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 53 11          \{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 53 11          \{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 53 d2          \{vex\} vpdpwssds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 53 d2          \{vex\} vpdpwssds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 53 11          \{vex\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 53 11          \{vex\} vpdpwssds \(%ecx\),%xmm4,%xmm2
  +[a-f0-9]+:   62 f2 5d 08 50 d2       vpdpbusd %xmm2,%xmm4,%xmm2
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni.d b/gas/testsuite/gas/i386/x86-64-avx-vnni.d
index c4474739ed8a8426dbcd5f71df612c37f4cae5c2..6b3acab5d549fdd92166e1a1e5bfe5dd617eecc2 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-avx-vnni.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-vnni.d
@@ -9,31 +9,31 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:   62 d2 5d 08 50 d4       vpdpbusd %xmm12,%xmm4,%xmm2
  +[a-f0-9]+:   62 d2 5d 08 50 d4       vpdpbusd %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 c2 59 50 d4          \{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 c2 59 50 d4          \{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 50 11          \{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 50 11          \{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 c2 59 50 d4          \{vex\} vpdpbusd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 c2 59 50 d4          \{vex\} vpdpbusd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 50 11          \{vex\} vpdpbusd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 50 11          \{vex\} vpdpbusd \(%rcx\),%xmm4,%xmm2
  +[a-f0-9]+:   62 b2 5d 08 50 d6       vpdpbusd %xmm22,%xmm4,%xmm2
  +[a-f0-9]+:   62 d2 5d 08 52 d4       vpdpwssd %xmm12,%xmm4,%xmm2
  +[a-f0-9]+:   62 d2 5d 08 52 d4       vpdpwssd %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 c2 59 52 d4          \{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 c2 59 52 d4          \{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 52 11          \{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 52 11          \{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 c2 59 52 d4          \{vex\} vpdpwssd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 c2 59 52 d4          \{vex\} vpdpwssd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 52 11          \{vex\} vpdpwssd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 52 11          \{vex\} vpdpwssd \(%rcx\),%xmm4,%xmm2
  +[a-f0-9]+:   62 b2 5d 08 52 d6       vpdpwssd %xmm22,%xmm4,%xmm2
  +[a-f0-9]+:   62 d2 5d 08 51 d4       vpdpbusds %xmm12,%xmm4,%xmm2
  +[a-f0-9]+:   62 d2 5d 08 51 d4       vpdpbusds %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 c2 59 51 d4          \{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 c2 59 51 d4          \{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 51 11          \{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 51 11          \{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 c2 59 51 d4          \{vex\} vpdpbusds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 c2 59 51 d4          \{vex\} vpdpbusds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 51 11          \{vex\} vpdpbusds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 51 11          \{vex\} vpdpbusds \(%rcx\),%xmm4,%xmm2
  +[a-f0-9]+:   62 b2 5d 08 51 d6       vpdpbusds %xmm22,%xmm4,%xmm2
  +[a-f0-9]+:   62 d2 5d 08 53 d4       vpdpwssds %xmm12,%xmm4,%xmm2
  +[a-f0-9]+:   62 d2 5d 08 53 d4       vpdpwssds %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 c2 59 53 d4          \{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 c2 59 53 d4          \{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 53 11          \{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2
- +[a-f0-9]+:   c4 e2 59 53 11          \{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 c2 59 53 d4          \{vex\} vpdpwssds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 c2 59 53 d4          \{vex\} vpdpwssds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 53 11          \{vex\} vpdpwssds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:   c4 e2 59 53 11          \{vex\} vpdpwssds \(%rcx\),%xmm4,%xmm2
  +[a-f0-9]+:   62 b2 5d 08 53 d6       vpdpwssds %xmm22,%xmm4,%xmm2
  +[a-f0-9]+:   62 d2 5d 08 50 d4       vpdpbusd %xmm12,%xmm4,%xmm2
 #pass

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 08d16f91e47736e3e73b73027557ba6757f1f247..0720b95086946373be9e4ad1e21f11e6304df2de 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2020-10-26  Lili Cui  <lili.cui@intel.com>
+
+       * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix. 
+
 2020-10-22  H.J. Lu  <hongjiu.lu@intel.com>
 
        * po/es.po: Remove the duplicated entry.

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 068858b1e7725e96a7d2109d8311b80c7897daa5..9338b1f3758a76b3e0f3f197f8d038452adce939 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11091,7 +11091,6 @@ putop (const char *in_template, int sizeflag)
                  *obufp++ = 'v';
                  *obufp++ = 'e';
                  *obufp++ = 'x';
-                 *obufp++ = '3';
                  *obufp++ = '}';
                }
              else if (rex & REX_W)