prepare LiteScope signals for debug

diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py
index e5b67373b8af98d8f4aee30abe13cb7e9d27569c..2e7b2bde6ea46331b7dd9f8ccbd923263514763c 100644 (file)
--- a/liteeth/core/arp.py
+++ b/liteeth/core/arp.py
@@ -37,8 +37,7 @@ class LiteEthARPTX(Module):
                counter = Counter(max=arp_packet_length)
                self.submodules += counter
 
-               fsm = FSM(reset_state="IDLE")
-               self.submodules += fsm
+               self.submodules.fsm = fsm = FSM(reset_state="IDLE")
                fsm.act("IDLE",
                        sink.ack.eq(1),
                        counter.reset.eq(1),
@@ -91,8 +90,7 @@ class LiteEthARPRX(Module):
                self.comb += Record.connect(self.sink, depacketizer.sink)
                sink = depacketizer.source
 
-               fsm = FSM(reset_state="IDLE")
-               self.submodules += fsm
+               self.submodules.fsm = fsm = FSM(reset_state="IDLE")
                fsm.act("IDLE",
                        sink.ack.eq(1),
                        If(sink.stb & sink.sop,
@@ -160,8 +158,7 @@ class LiteEthARPTable(Module):
                cached_ip_address = Signal(32)
                cached_mac_address = Signal(48)
 
-               fsm = FSM(reset_state="IDLE")
-               self.submodules += fsm
+               self.submodules.fsm = fsm = FSM(reset_state="IDLE")
                fsm.act("IDLE",
                        # Note: for simplicicy, if APR table is busy response from arp_rx
                        # is lost. This is compensated by the protocol (retrys)

diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py
index 24120ed14661bac92f415334da4468ad767c07b4..b0e8f35edd65d409bd1a6e3376ab68c6b706b620 100644 (file)
--- a/liteeth/core/ip.py
+++ b/liteeth/core/ip.py
@@ -75,8 +75,7 @@ class LiteEthIPTX(Module):
 
                target_mac = Signal(48)
 
-               fsm = FSM(reset_state="IDLE")
-               self.submodules += fsm
+               self.submodules.fsm = fsm = FSM(reset_state="IDLE")
                fsm.act("IDLE",
                        sink.ack.eq(1),
                        If(sink.stb & sink.sop,
@@ -125,8 +124,7 @@ class LiteEthIPRX(Module):
                self.submodules += checksum
                self.comb += checksum.header.eq(depacketizer.header)
 
-               fsm = FSM(reset_state="IDLE")
-               self.submodules += fsm
+               self.submodules.fsm = fsm = FSM(reset_state="IDLE")
                fsm.act("IDLE",
                        sink.ack.eq(1),
                        If(sink.stb & sink.sop,

diff --git a/liteeth/core/udp.py b/liteeth/core/udp.py
index f00429a670016b4c93dc278d0e4345eaf9125e34..d2f999537f01650179bbda38affb6a2e73f4e790 100644 (file)
--- a/liteeth/core/udp.py
+++ b/liteeth/core/udp.py
@@ -38,8 +38,7 @@ class LiteEthUDPTX(Module):
                ]
                sink = packetizer.source
 
-               fsm = FSM(reset_state="IDLE")
-               self.submodules += fsm
+               self.submodules.fsm = fsm = FSM(reset_state="IDLE")
                fsm.act("IDLE",
                        sink.ack.eq(1),
                        If(sink.stb & sink.sop,
@@ -67,8 +66,7 @@ class LiteEthUDPRX(Module):
                self.comb += Record.connect(self.sink, depacketizer.sink)
                sink = depacketizer.source
 
-               fsm = FSM(reset_state="IDLE")
-               self.submodules += fsm
+               self.submodules.fsm = fsm = FSM(reset_state="IDLE")
                fsm.act("IDLE",
                        sink.ack.eq(1),
                        If(sink.stb & sink.sop,

diff --git a/targets/udpip.py b/targets/udpip.py
index 0019c684cdd418be8e40403e23aa0eaebceab365..e584c90fce3adac768bca0e1f1b5b672b3edccb8 100644 (file)
--- a/targets/udpip.py
+++ b/targets/udpip.py
@@ -164,7 +164,7 @@ class UDPIPSoC(GenSoC, AutoCSR):
        default_platform = "kc705"
        csr_map = {
                "ethphy":                       11,
-               "udpipcore":            12,
+               "udpip_core":           12,
                "bist_generator":       13
        }
        csr_map.update(GenSoC.csr_map)
@@ -175,13 +175,13 @@ class UDPIPSoC(GenSoC, AutoCSR):
 
                # Ethernet PHY and UDP/IP
                self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
-               self.submodules.udpipcore = LiteEthUDPIPCore(self.ethphy, 0x12345678, 0x10e2d5000000)
+               self.submodules.udpip_core = LiteEthUDPIPCore(self.ethphy, 0x12345678, 0x10e2d5000000)
 
                # BIST
                self.submodules.bist_generator = UDPIPBISTGenerator()
                self.comb += [
-                       Record.connect(self.bist_generator.source, self.udpipcore.sink),
-                       self.udpipcore.source.ack.eq(1)
+                       Record.connect(self.bist_generator.source, self.udpip_core.sink),
+                       self.udpip_core.source.ack.eq(1)
                ]
 
 class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
@@ -192,9 +192,32 @@ class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
        def __init__(self, platform):
                UDPIPSoC.__init__(self, platform)
 
+               self.udpip_core_udp_rx_fsm_state = Signal(4)
+               self.udpip_core_udp_tx_fsm_state = Signal(4)
+               self.udpip_core_ip_rx_fsm_state = Signal(4)
+               self.udpip_core_ip_tx_fsm_state = Signal(4)
+               self.udpip_core_arp_rx_fsm_state = Signal(4)
+               self.udpip_core_arp_tx_fsm_state = Signal(4)
+
                debug = (
-                       Signal(),
-                       Signal()
+                       self.udpip_core.mac.core.sink.stb,
+                       self.udpip_core.mac.core.sink.sop,
+                       self.udpip_core.mac.core.sink.eop,
+                       self.udpip_core.mac.core.sink.ack,
+                       self.udpip_core.mac.core.sink.data,
+
+                       self.udpip_core.mac.core.source.stb,
+                       self.udpip_core.mac.core.source.sop,
+                       self.udpip_core.mac.core.source.eop,
+                       self.udpip_core.mac.core.source.ack,
+                       self.udpip_core.mac.core.source.data,
+
+                       self.udpip_core_udp_rx_fsm_state,
+                       self.udpip_core_udp_tx_fsm_state,
+                       self.udpip_core_ip_rx_fsm_state,
+                       self.udpip_core_ip_tx_fsm_state,
+                       self.udpip_core_arp_rx_fsm_state,
+                       self.udpip_core_arp_tx_fsm_state
                )
 
                self.submodules.la = LiteScopeLA(debug, 2048)
@@ -203,6 +226,14 @@ class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
 
        def do_finalize(self):
                UDPIPSoC.do_finalize(self)
+               self.comb += [
+                       self.udpip_core_udp_rx_fsm_state.eq(self.udpip_core.udp.rx.fsm.state),
+                       self.udpip_core_udp_tx_fsm_state.eq(self.udpip_core.udp.tx.fsm.state),
+                       self.udpip_core_ip_rx_fsm_state.eq(self.udpip_core.ip.rx.fsm.state),
+                       self.udpip_core_ip_tx_fsm_state.eq(self.udpip_core.ip.tx.fsm.state),
+                       self.udpip_core_arp_rx_fsm_state.eq(self.udpip_core.arp.rx.fsm.state),
+                       self.udpip_core_arp_tx_fsm_state.eq(self.udpip_core.arp.tx.fsm.state)
+               ]
 
        def exit(self, platform):
                if platform.vns is not None:

diff --git a/test/test_udpip.py b/test/test_udpip.py
index 9aff6ac9302d6d07ed77a43e7420bda823a226b9..2bc3c8accf4e2fb974189afba3fe9982ef92b421 100644 (file)
--- a/test/test_udpip.py
+++ b/test/test_udpip.py
@@ -1,6 +1,9 @@
 from config import *
 import time
 
+from litescope.host.driver import LiteScopeLADriver
+la = LiteScopeLADriver(wb.regs, "la", debug=True)
+
 wb.open()
 regs = wb.regs
 ###
@@ -12,9 +15,22 @@ regs.bist_generator_dst_port.write(0x5678)
 regs.bist_generator_ip_address.write(0x12345678)
 regs.bist_generator_length.write(64)
 
-for i in range(16):
-       regs.bist_generator_start.write(1)
-       time.sleep(1)
+conditions = {}
+conditions = {
+       "udpip_core_mac_tx_cdc_sink_stb"        : 1
+}
+la.configure_term(port=0, cond=conditions)
+la.configure_sum("term")
+# Run Logic Analyzer
+la.run(offset=64, length=1024)
+
+regs.bist_generator_start.write(1)
+
+while not la.done():
+       pass
+
+la.upload()
+la.save("dump.vcd")
 
 ###
 wb.close()