[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Sat, 23 May 2020 20:52:31 +0000 (20:52 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sat, 23 May 2020 20:52:33 +0000 (21:52 +0100)
3a/d2cb245c5ce57fb9c5aaba79d7af6b7fe740f5 [new file with mode: 0644]

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+Date: Sat, 23 May 2020 20:52:31 +0000
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+X-Bugzilla-Severity: enhancement
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+Message-ID: <bug-336-13-4zxD29fCXl@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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