Use CSINC instead of CSEL to return 1 (AArch64)

From-SVN: r193452

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c03a235315a202bf13c34d49fba94e125920fc72..ac116172052d4a2296f3f472046bee702365bc1c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2012-11-12  Ian Bolton  <ian.bolton@arm.com>
+
+       * config/aarch64/aarch64.md (cmov<mode>_insn): Emit CSINC when
+       one of the alternatives is constant 1.
+       * config/aarch64/constraints.md: New constraint.
+       * config/aarch64/predicates.md: Rename predicate
+       aarch64_reg_zero_or_m1 to aarch64_reg_zero_or_m1_or_1.
+
 2012-11-12  Ian Bolton  <ian.bolton@arm.com>
 
        * config/aarch64/aarch64.md (*compare_neg<mode>): New pattern.

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 077a89e8d3ed4f5ab7cc9a65531e01435146d32f..a9a8b5f9c2a1abeaf3a3a8b4fdf934f31ab97d95 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1885,19 +1885,23 @@
 )
 
 (define_insn "*cmov<mode>_insn"
-  [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r")
+  [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r,r,r,r")
        (if_then_else:ALLI
         (match_operator 1 "aarch64_comparison_operator"
          [(match_operand 2 "cc_register" "") (const_int 0)])
-        (match_operand:ALLI 3 "aarch64_reg_zero_or_m1" "rZ,rZ,UsM,UsM")
-        (match_operand:ALLI 4 "aarch64_reg_zero_or_m1" "rZ,UsM,rZ,UsM")))]
-  ""
-  ;; Final alternative should be unreachable, but included for completeness
+        (match_operand:ALLI 3 "aarch64_reg_zero_or_m1_or_1" "rZ,rZ,UsM,rZ,Ui1,UsM,Ui1")
+        (match_operand:ALLI 4 "aarch64_reg_zero_or_m1_or_1" "rZ,UsM,rZ,Ui1,rZ,UsM,Ui1")))]
+  "!((operands[3] == const1_rtx && operands[4] == constm1_rtx)
+     || (operands[3] == constm1_rtx && operands[4] == const1_rtx))"
+  ;; Final two alternatives should be unreachable, but included for completeness
   "@
    csel\\t%<w>0, %<w>3, %<w>4, %m1
    csinv\\t%<w>0, %<w>3, <w>zr, %m1
    csinv\\t%<w>0, %<w>4, <w>zr, %M1
-   mov\\t%<w>0, -1"
+   csinc\\t%<w>0, %<w>3, <w>zr, %m1
+   csinc\\t%<w>0, %<w>4, <w>zr, %M1
+   mov\\t%<w>0, -1
+   mov\\t%<w>0, 1"
   [(set_attr "v8type" "csel")
    (set_attr "mode" "<MODE>")]
 )

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index fe613070f4e47a3d8988679a6802d836c739a958..dae4b94b71a32487a059ed5616d4b94e11b405d2 100644 (file)
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -102,6 +102,11 @@
   A constraint that matches the immediate constant -1."
   (match_test "op == constm1_rtx"))
 
+(define_constraint "Ui1"
+  "@internal
+  A constraint that matches the immediate constant +1."
+  (match_test "op == const1_rtx"))
+
 (define_constraint "Ui3"
   "@internal
   A constraint that matches the integers 0...4."

diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 6f79039647c24285b106e45a9716d7d4fd68afd5..80f6ce2cb37141513b564aaa55aa63f2bc5d5c1b 100644 (file)
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -31,11 +31,12 @@
        (ior (match_operand 0 "register_operand")
            (match_test "op == const0_rtx"))))
 
-(define_predicate "aarch64_reg_zero_or_m1"
+(define_predicate "aarch64_reg_zero_or_m1_or_1"
   (and (match_code "reg,subreg,const_int")
        (ior (match_operand 0 "register_operand")
            (ior (match_test "op == const0_rtx")
-                (match_test "op == constm1_rtx")))))
+                (ior (match_test "op == constm1_rtx")
+                     (match_test "op == const1_rtx"))))))
 
 (define_predicate "aarch64_fp_compare_operand"
   (ior (match_operand 0 "register_operand")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3cda5b6acaaeaaa37c6cc3d65c7d5acb6e947820..9c933702cb331289e7f725dc6b66dd10e51f632c 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2012-11-12  Ian Bolton  <ian.bolton@arm.com>
+
+       * gcc.target/aarch64/csinc-2.c: New test.
+
 2012-11-12  Ian Bolton  <ian.bolton@arm.com>
 
        * gcc.target/aarch64/cmn.c: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/csinc-2.c b/gcc/testsuite/gcc.target/aarch64/csinc-2.c
new file mode 100644 (file)
index 0000000..1b4eb7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/csinc-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int a, int b)
+{
+  return (a < b) ? 1 : 7;
+  /* { dg-final { scan-assembler "csinc\tw\[0-9\].*wzr" } } */
+}
+
+typedef long long s64;
+
+s64
+foo2 (s64 a, s64 b)