add RVV dependency on RV64GC to table

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index ec81658229bd0dd3fc4b562dc63bdf657f094e64..d33ff0524aa6ab0ee17123bbd41d16432910a423 100644 (file)
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -5,10 +5,10 @@
 |Draft SVP64   |5 (1)          |Scalable (2)         |yes                |yes                 |yes (3)              |no (4)                   |see (5)                |yes (6)               |yes (7)              |yes (8)                       |yes (9)              |yes (10)             |
 |VSX           |700+           |Packed SIMD          |no                 |no                  |no                   |yes (11)                 |yes                    |no                    |no                   |no                            |no                   |yes (12)             |
 |NEON          |~250 (13)      |Packed SIMD          |no                 |no                  |no                   |yes                      |yes                    |no                    |no                   |no                            |no                   |no                   |
-|SVE2          |~1000 (14)     |Predicated SIMD (15) |no (15)            |yes                 |no                   |yes                      |yes                    |no                    |yes (7)              |no                            |no                   |no                   |
-|AVX-512 (16)  |~1000s (17)    |Predicated SIMD      |no                 |yes                 |no                   |yes                      |yes                    |no                    |no                   |no                            |no                   |no                   |
-|RVV (18)      |~190           |Scalable (19)        |yes                |yes                 |no                   |yes                      |yes (20)               |no                    |yes                  |no                            |no                   |no                   |
-|Aurora SX (21)|~200 (22)      |Scalable (23)        |yes                |yes                 |no                   |yes                      |no                     |no                    |no                   |no                            |no                   |no                   |
+|SVE2          |~1000 (14)     |Predicated SIMD(15)  |no (15)            |yes                 |no                   |yes                      |yes                    |no                    |yes (7)              |no                            |no                   |no                   |
+|AVX512 (16)   |~1000s (17)    |Predicated SIMD      |no                 |yes                 |no                   |yes                      |yes                    |no                    |no                   |no                            |no                   |no                   |
+|RVV (18)      |~190 (19)      |Scalable (20)        |yes                |yes                 |no                   |yes                      |yes (21)               |no                    |yes                  |no                            |no                   |no                   |
+|Aurora SX (22)|~200 (23)      |Scalable (24)        |yes                |yes                 |no                   |yes                      |no                     |no                    |no                   |no                            |no                   |no                   |
 
 * (1): plus EXT001 24-bit prefixing. See [[sv/svp64]]
 * (2): A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
@@ -30,8 +30,9 @@
 * (16): [AVX512 Wikipedia](https://en.wikipedia.org/wiki/AVX-512), [Lifecycle of an instruction set](https://media.handmade-seattle.com/tom-forsyth/) including full slides
 * (17): difficult to exactly ascertain, contains subsets. Critically depends on ISA support from earlier x86 ISA subsets (several more thousand instructions). See [SIMD ISA listing](https://www.officedaytime.com/simd512e/)
 * (18): [RVV Spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc)
-* (19): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction).  However, like SVE2, the Maximum Vector length is a Silicon-partner choice, which creates similar limitations that SVP64 does not have.
-* (20): like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements.
-* (21): [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors
-* (22): [Aurora ISA guide](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508
-* (23): Like the original Cray Vectors, the ISA Vector Length is independent of the underlying hardware, however Generation 1 has 256 elements per Vector register (3.2.4 p24, Aurora ISA guide)
+* (19): RISC-V Vectors are not stand-alone, i.e. like SVE2 and AVX-512 are critically dependent on the Scalar ISA (an additional ~96 instructions for the Scalar RV64GC set (RV64GC is equivalent to the Linux Compliancy Level)
+* (20): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction).  However, like SVE2, the Maximum Vector length is a Silicon-partner choice, which creates similar limitations that SVP64 does not have.
+* (21): like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements.
+* (22): [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors
+* (23): [Aurora ISA guide](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508
+* (24): Like the original Cray Vectors, the ISA Vector Length is independent of the underlying hardware, however Generation 1 has 256 elements per Vector register (3.2.4 p24, Aurora ISA guide)