""",
}
+ def iter_clock_constraints(self):
+ for net_signal, port_signal, frequency in super().iter_clock_constraints():
+ # Skip any clock constraints placed on signals that are never used in the design.
+ # Otherwise, it will cause a crash in the vendor platform if it supports clock
+ # constraints on non-port nets.
+ if net_signal not in self._name_map:
+ continue
+ yield net_signal, port_signal, frequency
+
def toolchain_prepare(self, fragment, name, **kwargs):
# Restrict the name of the design to a strict alphanumeric character set. Platforms will
# interpolate the name of the design in many different contexts: filesystem paths, Python
# and to incorporate the nMigen version into generated code.
autogenerated = "Automatically generated by nMigen {}. Do not edit.".format(__version__)
- rtlil_text, name_map = rtlil.convert_fragment(fragment, name=name)
+ rtlil_text, self._name_map = rtlil.convert_fragment(fragment, name=name)
def emit_rtlil():
return rtlil_text
return " ".join(opts)
def hierarchy(signal, separator):
- return separator.join(name_map[signal][1:])
+ return separator.join(self._name_map[signal][1:])
def ascii_escape(string):
def escape_one(match):