soc_core: set csr to 0x00000000 when there is no wishbone

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 152a4a2c1f701d3b0a652cf080dbe993150f1b9e..512d0dc0cc656f9b1de861c85629f6501a7e75c9 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -205,6 +205,9 @@ class SoCCore(Module):
         if cpu_type == "None":
             cpu_type = None
 
+        if not with_wishbone:
+            self.soc_mem_map["csr"]  = 0x00000000
+
         self.cpu_type    = cpu_type
         self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)