Fixes in fsm detect/extract for better detection of non-fsm circuits

diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 6cd428a87dfdfbfc287adf97d95d64ed7779533f..a8ec19126a8464768cfba58dd40dcf949355a227 100644 (file)
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -161,7 +161,7 @@ struct FsmDetectPass : public Pass {
                        sig_at_port.clear();
                        for (auto &cell_it : module->cells)
                                for (auto &conn_it : cell_it.second->connections) {
-                                       if (ct.cell_output(cell_it.second->type, conn_it.first)) {
+                                       if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
                                                RTLIL::SigSpec sig = conn_it.second;
                                                assign_map.apply(sig);
                                                sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index dc3a9ec092b20cf922d80f47a17e1db97dee3516..9cba904a7b2b1c7d607e9e666ab6e83e294c0b68 100644 (file)
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -144,8 +144,8 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d
                return;
        }
 
-       assert(undef.width > 0);
-       assert(ce.stop_signals.check_all(undef));
+       log_assert(undef.width > 0);
+       log_assert(ce.stop_signals.check_all(undef));
 
        undef = undef.extract(0, 1);
        constval = undef;
@@ -361,7 +361,7 @@ struct FsmExtractPass : public Pass {
                        sig2trigger.clear();
                        for (auto &cell_it : module->cells)
                                for (auto &conn_it : cell_it.second->connections) {
-                                       if (ct.cell_output(cell_it.second->type, conn_it.first)) {
+                                       if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
                                                RTLIL::SigSpec sig = conn_it.second;
                                                assign_map.apply(sig);
                                                sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));