Re: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

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+From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date: Thu, 26 Mar 2020 12:59:16 +0000
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+To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
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+Subject: Re: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA
+ and RISC-V
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