builder: change call to get_sdram_phy_c_header and also pass timing_settings

diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index 7887f89580c071044dc8f046e89bb795a1ceb682..a5564470ef3f9d24dfb2d83e3f97351e55ccacd7 100644 (file)
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -60,10 +60,6 @@ class Builder:
         flash_boot_address = getattr(self.soc, "flash_boot_address", None)
         csr_regions = self.soc.get_csr_regions()
         constants = self.soc.get_constants()
-        if isinstance(self.soc, soc_sdram.SoCSDRAM) and self.soc._sdram_phy:
-            sdram_phy_settings = self.soc._sdram_phy[0].settings
-        else:
-            sdram_phy_settings = None
 
         buildinc_dir = os.path.join(self.output_dir, "software", "include")
         generated_dir = os.path.join(buildinc_dir, "generated")
@@ -97,10 +93,12 @@ class Builder:
             os.path.join(generated_dir, "csr.h"),
             cpu_interface.get_csr_header(csr_regions, constants))
 
-        if sdram_phy_settings is not None:
+        if isinstance(self.soc, soc_sdram.SoCSDRAM):
             write_to_file(
                 os.path.join(generated_dir, "sdram_phy.h"),
-                sdram_init.get_sdram_phy_c_header(sdram_phy_settings))
+                sdram_init.get_sdram_phy_c_header(
+                    self.soc.sdram.controller.settings.phy,
+                    self.soc.sdram.controller.settings.timing))
 
     def _generate_csr_csv(self):
         memory_regions = self.soc.get_memory_regions()