move footnote

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 75dfc06557215cd8d3020f7fa75e79dfb456e5f8..afcdac878b7f8795303956fcb5a7334d5081e040 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -123,7 +123,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 * No new Interrupt types are required.
   (**No modifications to existing Power ISA are required either**).
 * GPR FPR and CR Field Register numbers are extended to 128.  A future
-  version may extend to 256 or beyond or also extend VSX[^extend][^futurevsx]
+  version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx]
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)
 * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding,
   currently named "SVP64-Single" [^likeext001]