intro/explanation of C

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index ae49be19a0c24b29052d98b199efcacd032dc0c7..eb92d74f3b050d6b105e34227195fce9be44a34d 100644 (file)
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -1,6 +1,17 @@
 # 16 bit Compressed
 
-Similar to VLE (but without immediate-prefixing) this encoding is designed to fit on top of OpenPOWER ISA v3.0B when a "Modeswitch bit" is set (PCR is recommended). Note that it is *mutually exclusively incompatible* with OoenPOWER v3.1B "prefixing" due to using (requiring) both EXT000 and EXT001. Hypothetically it could be made to use anything other than EXT001, with some inconvenience (extra gates).  The incompatibility is "fixed" by swapping out of "Compressed" Mode and back into "Normal" (v3.1B) Mode, at runtime, as needed.
+Similar to VLE (but without immediate-prefixing) this encoding is designed
+to fit on top of OpenPOWER ISA v3.0B when a "Modeswitch" bit is set (PCR
+is recommended). Note that Compressed it is *mutually exclusively incompatible*
+with OoenPOWER v3.1B "prefixing" due to using (requiring) both EXT000
+and EXT001. Hypothetically it could be made to use anything other than
+EXT001, with some inconvenience (extra gates).  The incompatibility is
+"fixed" by swapping out of "Compressed" Mode and back into "Normal"
+(v3.1B) Mode, at runtime, as needed.
+
+Although initially intended to be augmented by Simple-V Prefixing, to
+add Vector context and predication, this Compressed Encoding is not
+critically dependent *on* SV Prefixing, and may be used stand-alone
 
 See: