+2019-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24485
+ * config/tc-i386.c (process_suffix): Issue a warning to IRET
+ without a suffix for .code16gcc.
+ * testsuite/gas/i386/jump16.s: Add tests for iretX.
+ * testsuite/gas/i386/jump16.d: Updated.
+ * testsuite/gas/i386/jump16.e: New file.
+
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add case for
/* exclude fldenv/frstor/fsave/fstenv */
&& i.tm.opcode_modifier.no_ssuf)
{
- i.suffix = stackop_size;
+ if (stackop_size == LONG_MNEM_SUFFIX
+ && i.tm.base_opcode == 0xcf)
+ {
+ /* stackop_size is set to LONG_MNEM_SUFFIX for the
+ .code16gcc directive to support 16-bit mode with
+ 32-bit address. For IRET without a suffix, generate
+ 16-bit IRET (opcode 0xcf) to return from an interrupt
+ handler. */
+ i.suffix = WORD_MNEM_SUFFIX;
+ as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
+ }
+ else
+ i.suffix = stackop_size;
}
else if (intel_syntax
&& !i.suffix
if (!add_prefix (ADDR_PREFIX_OPCODE))
return 0;
}
- /* stackop_size is set to LONG_MNEM_SUFFIX for the .code16gcc
- directive to support 16bit mode with 32-bit address. Since
- IRET (opcode 0xcf) in 16bit mode returns from an interrupt
- in 16bit mode, we shouldn't add DATA_PREFIX_OPCODE here. */
else if (i.suffix != QWORD_MNEM_SUFFIX
- && (stackop_size != LONG_MNEM_SUFFIX
- || i.tm.base_opcode != 0xcf)
&& !i.tm.opcode_modifier.ignoresize
&& !i.tm.opcode_modifier.floatmf
&& !i.tm.opcode_modifier.vex
#name: i386 jump16
#objdump: -drw -mi8086
+#warning_output: jump16.e
.*: file format .*i386.*
[ ]*[a-f0-9]+: ea 00 00 90 90 ljmp \$0x9090,\$0x0 f2: (R_386_)?16 xxx
[ ]*[a-f0-9]+: cf iret
[ ]*[a-f0-9]+: cf iret
+[ ]*[a-f0-9]+: 66 cf iretl
+[ ]*[a-f0-9]+: cf iret
+[ ]*[a-f0-9]+: cf iret
+[ ]*[a-f0-9]+: 66 cf iretl
#pass