+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
+ arc_opcode_len.
+
2016-11-03 Graham Markall <graham.markall@embecosm.com>
* config/tc-arc.c (struct arc_insn): Replace short_insn flag with
break;
case O_pcl:
reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
- if (ARC_SHORT (opcode->mask) || opcode->insn_class == JUMP)
+ if (arc_opcode_len (opcode) == 2
+ || opcode->insn_class == JUMP)
as_bad_where (frag_now->fr_file, frag_now->fr_line,
_("Unable to use @pcl relocation for insn %s"),
opcode->name);
insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
/* Instruction length. */
- insn->len = ARC_SHORT (opcode->mask) ? 2 : 4;
+ insn->len = arc_opcode_len (opcode);
+ gas_assert (insn->len == 2 || insn->len == 4);
insn->insn = image;
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * opcode/arc.h (arc_opcode_len): Declare.
+ (ARC_SHORT): Delete.
+
2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
Andrew Waterman <andrew@sifive.com>
instructions. */
extern const struct arc_opcode arc_opcodes[];
+/* Return length of an instruction represented by OPCODE, in bytes. */
+extern int arc_opcode_len (const struct arc_opcode *opcode);
+
/* CPU Availability. */
#define ARC_OPCODE_NONE 0x0000
#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
#define ARC_XMAC 0x1000
#define ARC_CRC 0x1000
-/* A macro to check for short instructions. */
-#define ARC_SHORT(mask) \
- (((mask) & 0xFFFF0000) ? 0 : 1)
-
/* The operands table is an array of struct arc_operand. */
struct arc_operand
{
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
+ with arc_opcode_len.
+ (find_format_long_instructions): Likewise.
+ * arc-opc.c (arc_opcode_len): New function.
+
2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-nps400-tbl.h: Fix some instruction masks.
opcode = &arc_table[i++];
- if (ARC_SHORT (opcode->mask) && (insn_len == 2))
+ if ((arc_opcode_len (opcode) == 2) && (insn_len == 2))
{
if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
continue;
}
- else if (!ARC_SHORT (opcode->mask) && (insn_len == 4))
+ else if ((arc_opcode_len (opcode) == 4) && (insn_len == 4))
{
if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
continue;
opcode = &arc_long_opcodes[i].base_opcode;
- if (ARC_SHORT (opcode->mask) && (*insn_len == 2))
+ if ((arc_opcode_len (opcode) == 2) && (*insn_len == 2))
{
if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
continue;
}
- else if (!ARC_SHORT (opcode->mask) && (*insn_len == 4))
+ else if ((arc_opcode_len (opcode) == 4) && (*insn_len == 4))
{
if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
continue;
};
const unsigned arc_num_long_opcodes = ARRAY_SIZE (arc_long_opcodes);
+
+/* Return length of instruction represented by OPCODE in bytes. */
+
+int
+arc_opcode_len (const struct arc_opcode *opcode)
+{
+ if (opcode->mask < 0x10000ull)
+ return 2;
+ return 4;
+}