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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index a7a8dd46e02d6b1684a28debd82f381ed5f40c32..4b392ee0076f8cdda6c13116b8f0bbb6fb26f94f 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -584,7 +584,7 @@ schedules to more than just registers
 
 OpenCAPI is a deterministic high-performance, high-bandwidth, low-latency
 cache-coherent Memory-access Protocol that is integrated into IBM's Supercomputing-class POWER9 and POWER10 processors. POWER10 *only*
-has OpenCAPI Memory interfaces, and requires an OpenCAPI-to-DDR4/5 Bridge PHY
+has OpenCAPI Memory interfaces, and requires an OMI-to-DDR4/5 Bridge PHY
 to connect to standard DIMMs.
 
 Extra-V appears to be a remarkable research project that, by leveraging