clarify basic principle

diff --git a/openpower/sv/rfc/Makefile b/openpower/sv/rfc/Makefile
index 23df8bb3b43636d8b17e097e6e52ce234a970551..bb2137c52c7be022ab2ff527e43894f4a8be317c 100644 (file)
--- a/openpower/sv/rfc/Makefile
+++ b/openpower/sv/rfc/Makefile
@@ -4,8 +4,8 @@ ls001.pdf: ls001.mdwn
        pandoc \
             -V margin-top=0.9in \
             -V margin-bottom=0.9in \
-            -V margin-left=0.5in \
-            -V margin-right=0.5in \
+            -V margin-left=0.4in \
+            -V margin-right=0.4in \
               -V fontsize=9pt \
               -V papersize=legal \
               -V linkcolor=blue \

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 8dd3d42bb552ef2ecbf0e75d036f980318e8b760..6ff623b83a4fabd7f1259f505d5a19c2ce0e83ce 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -69,15 +69,16 @@ Branch.
 
 # Basic principle
 
-The inspiration for this came from the fact that on examination of every
+The inspiration for Simple-V came from the fact that on examination of every
 Vector ISA pseudocode encountered the Vector operations were expressed
 as a for-loop on a Scalar element
 operation, and then both a Scalar **and** a Vector instruction was added.
-It felt natural to separate the two at both the ISA and the Hardware Level
+With Zero-Overhead Looping *already* being mainstream in DSPs for over three
+decades it felt natural to separate the looping at both the ISA and
+the Hardware Level
 and thus provide only Scalar instructions (instantly halving the number
-of instructions), leaving it up to implementors
-to implement Superscalar and Multi-Issue Micro-architectures at their
-discretion.
+of instructions), but rather than go the VLIW route (TI MSP Series)
+keep closely to existing Power ISA standard Scalar execution.
 
 Thus the basic principle of Simple-V is to provide a Precise-Interruptible
 Zero-Overhead Loop system[^zolc] with associated register "offsetting"