Add write transactions in the simulation testbench

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index a8d3c8d3f3c743197f459e0da339e7f16513fab6..df7d997fb2a7c17ab1305865712e26c802acaa9e 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -160,6 +160,11 @@ module simsoctb;
       wishbone_write(32'h00009000 >> 2, 8'h01); // DFII_CONTROL_SEL
       #2000;
 
+      // Write
+      wishbone_write(32'h10000000 >> 2, 32'h12345678);
+      #10000;
+      wishbone_write(32'h10000100 >> 2, 32'h00000000);
+      #10000;
       wishbone_read(32'h10000000 >> 2, tmp);
     end