Fix xilinx_dsp index cast

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 60e972615a73aebbc78c39794679e3f30f03b16c..51fd733d41afe058e889c78d832025fa738d6c34 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -11,7 +11,7 @@ match ffA
        select ffA->type.in($dff, $dffe)
        select param(ffA, \CLK_POLARITY).as_bool()
        // select nusers(port(ffA, \Q)) == 2
-       index <SigSpec> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool()
+       index <pool<SigBit>> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool()
        // DSP48E1 does not support clock inversion
        optional
 endmatch
@@ -25,7 +25,7 @@ match ffB
        select ffB->type.in($dff, $dffe)
        select param(ffB, \CLK_POLARITY).as_bool()
        // select nusers(port(ffB, \Q)) == 2
-       index <SigSpec> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool()
+       index <pool<SigBit>> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool()
        optional
 endmatch