ulx3s: Connect SDRAM clock

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 6d8a4e077c47c91f7f2e7cfc6cbe0841a81058d5..af1aa19e42bede3ffa04ecf283dddbe46098d5c7 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -45,6 +45,8 @@ class _CRG(Module):
                 o_Z=new_sdram_ps_clk)
             sdram_ps_clk = new_sdram_ps_clk
         self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk)
+        sdram_clock = platform.request("sdram_clock")
+        self.comb += sdram_clock.eq(sdram_ps_clk)
 
         # Stop ESP32 from resetting FPGA
         wifi_gpio0 = platform.request("wifi_gpio0")