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litesata: fix permissions and imports
authorSebastien Bourdeauducq <sb@m-labs.hk>
Wed, 4 Mar 2015 00:46:24 +0000 (00:46 +0000)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Wed, 4 Mar 2015 00:46:24 +0000 (00:46 +0000)
misoclib/mem/litesata/example_designs/build/.keep_me [new file with mode: 0644] patch | blob
misoclib/mem/litesata/example_designs/make.py [changed mode: 0644->0755] patch | blob | history
misoclib/mem/litesata/example_designs/platforms/verilog_backend.py patch | blob | history

diff --git a/misoclib/mem/litesata/example_designs/build/.keep_me b/misoclib/mem/litesata/example_designs/build/.keep_me
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py
old mode 100644 (file)
new mode 100755 (executable)
diff --git a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
index f531c901d1a1e120bb732c2fe291f0d8d6355147..7302a0eb215b6d28583e29348d89b9139a9d964a 100644 (file)
--- a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
+++ b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_DS
-from mibuild.xilinx_vivado import XilinxVivadoPlatform
+from mibuild.xilinx.common import CRG_DS
+from mibuild.xilinx.vivado import XilinxVivadoPlatform
 
 _io = [
        ("sys_clk", 0, Pins("X")),