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higher bits need to be checked for overflow not lower
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 29 Apr 2022 09:47:03 +0000 (10:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 29 Apr 2022 09:47:03 +0000 (10:47 +0100)
after swapping RC and RA, RC is now in the higher bits of divmod2du

openpower/isa/svfixedarith.mdwn patch | blob | history

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index cf8834502445c0aa20646abe2144edc35c917b19..cd2b320a84916d7bb4876ed39e8b99e26760af64 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -29,7 +29,7 @@ Pseudo-code:
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
-    if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
+    if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
         dividend[0:(XLEN*2)-1] <- (RC) || (RA)
         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
         result <- dividend / divisor