remive svfixedload.mdwn. requires scalar fixed load to be

added to Power ISA 3 *scalar* instructions

diff --git a/openpower/isa/svfixedload.mdwn b/openpower/isa/svfixedload.mdwn
deleted file mode 100644 (file)
index d97eca9..0000000
--- a/openpower/isa/svfixedload.mdwn
+++ /dev/null
@@ -1,191 +0,0 @@
-<!-- This defines SVP64 Shifted Load instructions -->
-<!-- They are augmented variants of v3.0B Load instructions -->
-<!-- and are designed to help with Cooley-Tukey FFT/DCT -->
-
-# Load Byte and Zero
-
-SVD-Form
-
-* lbzsh RT,SVD(RA),RC
-
-Pseudo-code:
-
-    b <- (RA|0)
-    n <- (RC)[58:63]
-    EA <- b + SHL64(srcstep * EXTS(SVD), n)
-    RT <- [0]*56 || MEM(EA, 1)
-
-Special Registers Altered:
-
-    None
-
-# Load Byte and Zero with Update
-
-SVD-Form
-
-* lbzush RT,SVD(RA),RC
-
-Pseudo-code:
-
-    n <- (RC)[58:63]
-    EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
-    RT <- [0] * 56 || MEM(EA, 1)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword and Zero
-
-SVD-Form
-
-* lhzsh RT,SVD(RA),RC
-
-Pseudo-code:
-
-    b <- (RA|0)
-    n <- (RC)[58:63]
-    EA <- b + SHL64(srcstep * EXTS(SVD), n)
-    RT <- [0] * 48 || MEM(EA, 2)
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword and Zero with Update
-
-SVD-Form
-
-* lhzush RT,SVD(RA),RC
-
-Pseudo-code:
-
-    n <- (RC)[58:63]
-    EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
-    RT <- [0] * 48 || MEM(EA, 2)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword Algebraic
-
-SVD-Form
-
-* lhash RT,SVD(RA),RC
-
-Pseudo-code:
-
-    b <- (RA|0)
-    n <- (RC)[58:63]
-    EA <- b + SHL64(srcstep * EXTS(SVD), n)
-    RT <- EXTS(MEM(EA, 2))
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword Algebraic with Update
-
-SVD-Form
-
-* lhaush RT,SVD(RA),RC
-
-Pseudo-code:
-
-    n <- (RC)[58:63]
-    EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
-    RT <- EXTS(MEM(EA, 2))
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Word and Zero
-
-SVD-Form
-
-* lwzsh RT,SVD(RA),RC
-
-Pseudo-code:
-
-    b <- (RA|0)
-    n <- (RC)[58:63]
-    EA <- b + SHL64(srcstep * EXTS(SVD), n)
-    RT <- [0] * 32 || MEM(EA, 4)
-
-Special Registers Altered:
-
-    None
-
-# Load Word and Zero with Update
-
-SVD-Form
-
-* lwzush RT,SVD(RA),RC
-
-Pseudo-code:
-
-    n <- (RC)[58:63]
-    EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
-    RT <- [0]*32 || MEM(EA, 4)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Word Algebraic
-
-SVDS-Form
-
-* lwash RT,SVDS(RA),RC
-
-Pseudo-code:
-
-    b <- (RA|0)
-    n <- (RC)[58:63]
-    EA <- b + SHL64(srcstep * EXTS(SVDS || 0b00), n)
-    RT <- EXTS(MEM(EA, 4))
-
-Special Registers Altered:
-
-    None
-
-# Load Doubleword
-
-SVDS-Form
-
-* ldsh RT,SVDS(RA),RC
-
-Pseudo-code:
-
-    b <- (RA|0)
-    n <- (RC)[58:63]
-    EA <- b + SHL64(srcstep * EXTS(SVDS || 0b00), n)
-    RT <- MEM(EA, 8)
-
-Special Registers Altered:
-
-    None
-
-# Load Doubleword with Update Indexed
-
-SVDS-Form
-
-* ldush RT,SVDS(RA),RC
-
-Pseudo-code:
-
-    n <- (RC)[58:63]
-    EA <- (RA) + SHL64(srcstep * EXTS(SVDS || 0b00), n)
-    RT <- MEM(EA, 8)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-