Use meaningful class names

diff --git a/examples/corelogic_conv.py b/examples/corelogic_conv.py
index dd9c986b7c7a9740c9d185e61408376f652671c4..d82f8af1cf472d6c3844e39b2c8008b1072f8b62 100644 (file)
--- a/examples/corelogic_conv.py
+++ b/examples/corelogic_conv.py
@@ -1,8 +1,8 @@
 from migen.fhdl import verilog
 from migen.corelogic import divider
 
-d1 = divider.Inst(16)
-d2 = divider.Inst(16)
+d1 = divider.Divider(16)
+d2 = divider.Divider(16)
 frag = d1.get_fragment() + d2.get_fragment()
 o = verilog.convert(frag, {
        d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index b1df3b72460bbae855620aac308fa67bb759d0a6..041894b1100c907f2b1ec0dd9c09cb0909df4a9d 100644 (file)
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -29,7 +29,7 @@ class Arbiter:
        def __init__(self, masters, target):
                self.masters = masters
                self.target = target
-               self.rr = roundrobin.Inst(len(self.masters))
+               self.rr = roundrobin.RoundRobin(len(self.masters))
 
        def get_fragment(self):
                comb = []

diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py
index 497cac68250f57a1198710a67365969b1547af81..a0cd56292fba93a3eecb98e471e3d46fb1d77f38 100644 (file)
--- a/migen/bus/wishbone2csr.py
+++ b/migen/bus/wishbone2csr.py
@@ -3,11 +3,11 @@ from migen.bus import csr
 from migen.fhdl.structure import *
 from migen.corelogic import timeline
 
-class Inst():
+class WB2CSR():
        def __init__(self):
                self.wishbone = wishbone.Slave("to_csr")
                self.csr = csr.Master("from_wishbone")
-               self.timeline = timeline.Inst(self.wishbone.cyc_i & self.wishbone.stb_i,
+               self.timeline = timeline.Timeline(self.wishbone.cyc_i & self.wishbone.stb_i,
                        [(1, [self.csr.we_o.eq(self.wishbone.we_i)]),
                        (2, [self.wishbone.ack_o.eq(1)]),
                        (3, [self.wishbone.ack_o.eq(0)])])

diff --git a/migen/corelogic/divider.py b/migen/corelogic/divider.py
index fb2214754fa402896230a65b94027abcf55c9f99..50b4af18f7d30cc17f326a45a7886d0e47c2c2fd 100644 (file)
--- a/migen/corelogic/divider.py
+++ b/migen/corelogic/divider.py
@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 
-class Inst:
+class Divider:
        def __init__(self, w):
                self.w = w
                

diff --git a/migen/corelogic/roundrobin.py b/migen/corelogic/roundrobin.py
index af1e057ddaace2aee4e2b27b24e72ba6a6d03fd9..1f0e5527d0e34b7be3fef1aa9fecadbf5929931c 100644 (file)
--- a/migen/corelogic/roundrobin.py
+++ b/migen/corelogic/roundrobin.py
@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 
-class Inst:
+class RoundRobin:
        def __init__(self, n):
                self.n = n
                self.bn = bits_for(self.n-1)

diff --git a/migen/corelogic/timeline.py b/migen/corelogic/timeline.py
index f47e188f54ce6bfd939babb3ab18f013bf7aafcf..0bbbdd1bfae48837392864f09a19cca51d2daaa9 100644 (file)
--- a/migen/corelogic/timeline.py
+++ b/migen/corelogic/timeline.py
@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 
-class Inst:
+class Timeline:
        def __init__(self, trigger, events):
                self.trigger = trigger
                self.events = events

diff --git a/migen/flow/ala.py b/migen/flow/ala.py
index 649c8cf6579664c84246b77896cd611f1c1dcae2..e472f54459cad1e92990eb14ab1550e869cb4f74 100644 (file)
--- a/migen/flow/ala.py
+++ b/migen/flow/ala.py
@@ -60,7 +60,7 @@ class NE(_SimpleBinary):
 
 class DivMod(Actor):
        def __init__(self, width):
-               self.div = divider.Inst(width)
+               self.div = divider.Divider(width)
                Actor.__init__(self,
                        SchedulingModel(SchedulingModel.SEQUENTIAL, width),
                        ("operands", Sink, [("dividend", self.div.dividend_i), ("divisor", self.div.divisor_i)]),