i965: Fix render target read domains.

We were asking for something illegal (write_domain != 0 && read_domains !=
write_domain) because at the time of writing the region surfaces were used
for texturing occasionally as well, and we weren't really clear on the model
GEM was going to use.

This reliably triggered a kernel bug with domain handling, resulting in
oglconform mustpass.c failure.  Of course, it only became visible after
01bc4d441fd6821ad9fc20d5e9544e4e587e4ff0 cleaned up some gratuitous flushing.

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 3593988f8d274377232bdd7e4f28e62f674dea0c..654adcd13176437b7fc22bd710ae02871775ede9 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -389,8 +389,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
          * a more restrictive relocation to emit.
          */
         dri_bo_emit_reloc(brw->wm.surf_bo[unit],
-                          I915_GEM_DOMAIN_RENDER |
-                          I915_GEM_DOMAIN_SAMPLER,
+                          I915_GEM_DOMAIN_RENDER,
                           I915_GEM_DOMAIN_RENDER,
                           0,
                           offsetof(struct brw_surface_state, ss1),