sim working

diff --git a/lib/sata/k7sataphy/ctrl.py b/lib/sata/k7sataphy/ctrl.py
index 07b541bd75558d08babfaf156c80281a75418b96..983980a15d8601943a63889bf01a3cf8c644e40c 100644 (file)
--- a/lib/sata/k7sataphy/ctrl.py
+++ b/lib/sata/k7sataphy/ctrl.py
@@ -83,9 +83,14 @@ class K7SATAPHYHostCtrl(Module):
                fsm.act("AWAIT_NO_COMWAKE",
                        gtx.txelecidle.eq(1),
                        If(~gtx.rxcomwakedet,
-                               NextState("AWAIT_ALIGN")
+                               NextState("RESET_CRG")
                        )
                )
+               fsm.act("RESET_CRG",
+                       gtx.txelecidle.eq(0),
+                       crg.reset.eq(1),
+                       NextState("AWAIT_ALIGN")
+               )
                fsm.act("AWAIT_ALIGN",
                        gtx.txelecidle.eq(0),
                        gtx.rxalign.eq(1),
@@ -99,14 +104,12 @@ class K7SATAPHYHostCtrl(Module):
                        gtx.txelecidle.eq(0),
                        self.txdata.eq(ALIGN_VAL),
                        self.txcharisk.eq(0b0001),
-                       If(non_align_cnt == 3,
+                       If(non_align_cnt == 15,
                                NextState("READY")
                        )
                )
                fsm.act("READY",
                        gtx.txelecidle.eq(0),
-                       self.txdata.eq(SYNC_VAL),
-                       self.txcharisk.eq(0b0001),
                        If(gtx.rxelecidle,
                                NextState("RESET")
                        ),
@@ -210,9 +213,14 @@ class K7SATAPHYDeviceCtrl(Module):
                        gtx.txelecidle.eq(1),
                        gtx.txcomwake.eq(1),
                        If(gtx.txcomfinish,
-                               NextState("SEND_ALIGN")
+                               NextState("RESET_CRG")
                        )
                )
+               fsm.act("RESET_CRG",
+                       gtx.txelecidle.eq(0),
+                       crg.reset.eq(1),
+                       NextState("SEND_ALIGN")
+               )
                fsm.act("SEND_ALIGN",
                        gtx.txelecidle.eq(0),
                        gtx.rxalign.eq(1),
@@ -225,8 +233,6 @@ class K7SATAPHYDeviceCtrl(Module):
                        )
                )
                fsm.act("READY",
-                       self.txdata.eq(SYNC_VAL),
-                       self.txcharisk.eq(0b0001),
                        gtx.txelecidle.eq(0),
                        NextState("READY"),
                        If(gtx.rxelecidle,

diff --git a/lib/sata/k7sataphy/gtx.py b/lib/sata/k7sataphy/gtx.py
index f307139233af61fc357d805d1620188f33d15b1f..b2eed8d287e69131bd7a6cf8ca76d33c5cd4bf00 100644 (file)
--- a/lib/sata/k7sataphy/gtx.py
+++ b/lib/sata/k7sataphy/gtx.py
@@ -239,7 +239,7 @@ class K7SATAPHYGTX(Module):
                                        "p_RX_DISPERR_SEQ_MATCH":"TRUE",
                                        "p_DEC_MCOMMA_DETECT":"TRUE",
                                        "p_DEC_PCOMMA_DETECT":"TRUE",
-                                       "p_DEC_VALID_COMMA_ONLY":"FALSE",
+                                       "p_DEC_VALID_COMMA_ONLY":"TRUE",
 
                                # RX Clock Correction Attributes
                                        "p_CBCC_DATA_SOURCE_SEL":"DECODED",

diff --git a/targets/test.py b/targets/test.py
index 28b97cbf771af412f22edc364d9d5c5c5342c16c..2af3bde30ee231fa534eb27a900cdb1c9e0731e8 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -95,6 +95,14 @@ class TestDesign(UART2WB):
                self.submodules.crg = _CRG(platform)
 
                self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True)
+               self.comb += [
+                       self.sataphy_host.sink.stb.eq(1),
+                       self.sataphy_host.sink.d.eq(0x12345678)
+               ]
                self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
+               self.comb += [
+                       self.sataphy_device.sink.stb.eq(1),
+                       self.sataphy_device.sink.d.eq(0x12345678)
+               ]
 
 default_subtarget = TestDesign