;; Special constraints for SH machine description:
;;
-;; t -- T
-;; x -- mac
-;; l -- pr
+;; t -- T
+;; x -- mac
+;; l -- pr
;; z -- r0
;;
;; Special formats used for outputting SH instructions:
;;
;; %. -- print a .s if insn needs delay slot
;; %# -- output a nop if there is nothing to put in the delay slot
-;; %R -- print the lsw arg of a double,
+;; %R -- print the lsw arg of a double,
;; %S -- print the msw arg of a double
;; %O -- print a constant without the #
;; %M -- print a constant as its negative
;; general_movdst_operand -- operand is valid move destination
;; general_movsrc_operand -- operand is valid move source
;; logical_operand -- operand is valid source for logical op
-;; pop_operand -- operand is a pop from the stack
;; system_reg_operand -- operand is MACL, MACH, or PR
;; -------------------------------------------------------------------------
;; Attributes
; Target CPU.
(define_attr "cpu" "sh0,sh1,sh2,sh3"
- (const (symbol_ref "sh_cpu")))
+ (const (symbol_ref "sh_cpu_attr")))
;;
;; cbranch conditional branch instructions
;; rte return from exception
;; sfunc special function call with known used registers
-(define_attr "type"
+(define_attr "type"
"cbranch,jump,arith,other,load,store,move,smpy,dmpy,return,pload,pcload,rte,sfunc"
(const_string "other"))
-; If a conditional branch destination is within -252..258 bytes away
+; If a conditional branch destination is within -252..258 bytes away
; from the instruction it can be 2 bytes long. Something in the
; range -4090..4100 bytes can be 6 bytes long. All other conditional
; branches are 16 bytes long.
; length. This is because shorten_branches starts with the largest
; instruction size and then tries to reduce them.
-(define_attr "length" ""
+(define_attr "length" ""
(cond [(eq_attr "type" "cbranch")
(if_then_else (and (ge (minus (match_dup 0) (pc))
(const_int -252))
;; (define_function_unit {name} {num-units} {n-users} {test}
;; {ready-delay} {issue-delay} [{conflict-list}])
-
+
(define_function_unit "memory" 1 0 (eq_attr "type" "load,pcload,pload") 2 2)
(define_function_unit "mpy" 1 0 (eq_attr "type" "smpy") 2 2)
(define_function_unit "mpy" 1 0 (eq_attr "type" "dmpy") 3 3)
(define_attr "interrupt_function" "no,yes"
(const (symbol_ref "pragma_interrupt")))
-(define_attr "in_delay_slot" "yes,no"
+(define_attr "in_delay_slot" "yes,no"
(cond [(eq_attr "type" "cbranch") (const_string "no")
(eq_attr "type" "pcload") (const_string "no")
(eq_attr "needs_delay_slot" "yes") (const_string "no")
(eq_attr "needs_delay_slot" "yes")
[(eq_attr "in_delay_slot" "yes") (nil) (nil)])
-(define_delay
+(define_delay
(eq_attr "type" "return")
- [(and (eq_attr "in_delay_slot" "yes")
+ [(and (eq_attr "in_delay_slot" "yes")
(and (ior (eq_attr "interrupt_function" "no")
(eq_attr "hit_stack" "no"))
(ior (eq_attr "interrupt_function" "yes")
(eq_attr "type" "!pload")))) (nil) (nil)])
-(define_delay
- (and (eq_attr "type" "cbranch")
+(define_delay
+ (and (eq_attr "type" "cbranch")
(eq_attr "cpu" "sh2,sh3"))
[(eq_attr "in_delay_slot" "yes") (nil) (nil)])
\f
""
"tst %1,%0")
+;; ??? Perhaps should only accept reg/constant if the register is reg 0.
+;; That would still allow reload to create cmpi instructions, but would
+;; perhaps allow forcing the constant into a register when that is better.
+
(define_insn "cmpeqsi_t"
[(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
(match_operand:SI 1 "arith_operand" "N,rI,r")))]
sh_compare_op1 = operands[1];
DONE;
}")
-
\f
;; -------------------------------------------------------------------------
;; Addition instructions
;; this should be a define split.
(define_insn "adddi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (plus:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "register_operand" "r")))
+ [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+ (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
+ (match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI 18))]
""
"clrt\;addc %R2,%R0\;addc %S2,%S0"
(define_insn "subdi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (minus:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "register_operand" "r")))
+ [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+ (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
+ (match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI 18))]
""
"clrt\;subc %R2,%R0\;subc %S2,%S0"
""
"sub %2,%0"
[(set_attr "type" "arith")])
-
\f
;; -------------------------------------------------------------------------
;; Division instructions
(clobber (reg:SI 17))
(clobber (reg:SI 6))
(clobber (reg:SI 4))
- (use (match_operand:SI 0 "register_operand" "r"))]
+ (use (match_operand:SI 0 "arith_reg_operand" "r"))]
""
"jsr @%0%#"
[(set_attr "type" "sfunc")
(clobber (reg:SI 6))
(clobber (reg:SI 4))
(use (match_dup 3))])
- (set (match_operand:SI 0 "general_operand" "=g")
+ (set (match_operand:SI 0 "general_operand" "=g")
(reg:SI 0))]
""
"operands[3] = gen_reg_rtx(SImode);")
(clobber (reg:SI 1))
(clobber (reg:SI 2))
(clobber (reg:SI 3))
- (use (match_operand:SI 0 "register_operand" "r"))]
+ (use (match_operand:SI 0 "arith_reg_operand" "r"))]
""
"jsr @%0%#"
[(set_attr "type" "sfunc")
(clobber (reg:SI 2))
(clobber (reg:SI 3))
(use (match_dup 3))])
- (set (match_operand:SI 0 "general_operand" "=g")
+ (set (match_operand:SI 0 "general_operand" "=g")
(reg:SI 0))]
""
"operands[3] = gen_reg_rtx(SImode);")
-
\f
;; -------------------------------------------------------------------------
;; Multiplication instructions
(clobber (reg:SI 3))
(clobber (reg:SI 2))
(clobber (reg:SI 1))
- (use (match_operand:SI 0 "register_operand" "r"))]
+ (use (match_operand:SI 0 "arith_reg_operand" "r"))]
""
"jsr @%0%#"
[(set_attr "type" "sfunc")
(clobber (reg:SI 2))
(clobber (reg:SI 1))
(use (match_dup 3))])
- (set (match_operand:SI 0 "general_operand" "=g")
+ (set (match_operand:SI 0 "general_operand" "=g")
(reg:SI 0))]
""
"operands[3] = gen_reg_rtx(SImode);")
-
+
(define_insn "mul_l"
[(set (reg:SI 21)
(mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
(reg:DI 20))]
"(TARGET_SH2) && 0"
"")
-
\f
;; -------------------------------------------------------------------------
;; Logical operations
""
"xor %2,%0"
[(set_attr "type" "arith")])
-
\f
;; -------------------------------------------------------------------------
;; Shifts and rotates
;;
;; shift left
-
(define_insn "ashlsi3_k"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
add %0,%0
shll%O2 %0")
-; ??? seperate pattern for shifts by any N. Turn this on to recognize shift
-; insns which aren't supported in the hardware. This will allow the combiner
-; to notice more patterns, but the down side is that the asm outputter will
-; have to emit several instructions for each shift which isn't possible in
-; the hardware, this makes scheduling perform badly.
-
(define_insn "ashlsi3_n"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
(match_operand:SI 2 "immediate_operand" "n")))
(clobber (reg:SI 18))]
- "0"
- "*return output_shift(\"shll\", operands[0], operands[2], ASHIFT);"
- [(set_attr "length" "12")
+ ""
+ "#"
+ [(set (attr "length")
+ (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
+ (const_string "2")
+ (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
+ (const_string "4")
+ (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
+ (const_string "6")]
+ (const_string "8")))
(set_attr "type" "arith")])
+(define_split
+ [(set (match_operand:SI 0 "arith_reg_operand" "")
+ (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
+ (match_operand:SI 2 "immediate_operand" "n")))
+ (clobber (reg:SI 18))]
+ ""
+ [(use (reg:SI 0))]
+ "
+{
+ gen_shifty_op (ASHIFT, operands);
+ DONE;
+}")
+
(define_expand "ashlsi3"
[(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "shiftby_operand" "")))
(clobber (reg:SI 18))])]
""
- "if (gen_shifty_op (ASHIFT, operands)) DONE; else FAIL;")
+ "if (! shiftby_operand (operands[2], SImode)) FAIL;")
;
; arithmetic shift right
[(set_attr "type" "arith")])
(define_insn "ashrsi2_16"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
(const_int 16)))]
""
"swap.w %1,%0\;exts.w %0,%0"
[(set_attr "length" "4")])
(define_insn "ashrsi2_31"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,!r")
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
+ (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0,!r")
(const_int 31)))
(clobber (reg:SI 18))]
""
}"
[(set_attr "length" "4,6")])
-
-
-
-
(define_insn "ashrsi3_n"
[(set (reg:SI 4)
(ashiftrt:SI (reg:SI 4)
""
"if (gen_shifty_op (ASHIFTRT, operands)) DONE; else FAIL;")
-; logical shift right
-;
+;; logical shift right
-(define_insn "lshrsi3_k"
- [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
- (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
- (match_operand:SI 2 "immediate_operand" "M,K")))
+;; ??? Only the single bit shift clobbers the T bit.
+
+(define_insn "lshrsi3_m"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ (match_operand:SI 2 "immediate_operand" "M")))
(clobber (reg:SI 18))]
- "CONST_OK_FOR_K (INTVAL (operands[2]))"
- "@
- shlr %0
- shlr%O2 %0")
+ "CONST_OK_FOR_M (INTVAL (operands[2]))"
+ "shlr %0")
-; ??? seperate pattern for shifts by any N. See ashlsi3_n.
+(define_insn "lshrsi3_k"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ (match_operand:SI 2 "immediate_operand" "K")))]
+ "CONST_OK_FOR_K (INTVAL (operands[2]))
+ && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
+ "shlr%O2 %0")
(define_insn "lshrsi3_n"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
(match_operand:SI 2 "immediate_operand" "n")))
(clobber (reg:SI 18))]
- "0"
- "* return output_shift (\"shlr\", operands[0], operands[2], LSHIFTRT);"
- [(set_attr "length" "12")
+ ""
+ "#"
+ [(set (attr "length")
+ (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
+ (const_string "2")
+ (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
+ (const_string "4")
+ (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
+ (const_string "6")]
+ (const_string "8")))
(set_attr "type" "arith")])
+(define_split
+ [(set (match_operand:SI 0 "arith_reg_operand" "")
+ (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
+ (match_operand:SI 2 "immediate_operand" "n")))
+ (clobber (reg:SI 18))]
+ ""
+ [(use (reg:SI 0))]
+ "
+{
+ gen_shifty_op (LSHIFTRT, operands);
+ DONE;
+}")
+
(define_expand "lshrsi3"
[(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "shiftby_operand" "")))
(clobber (reg:SI 18))])]
""
- "if (gen_shifty_op (LSHIFTRT, operands)) DONE; else FAIL;")
+ "if (! shiftby_operand (operands[2], SImode)) FAIL;")
(define_insn "ashldi3_k"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:SI 18))])]
-
+
""
- "{ if (GET_CODE (operands[2]) != CONST_INT
+ "{ if (GET_CODE (operands[2]) != CONST_INT
|| INTVAL (operands[2]) != 1) FAIL;} ")
(define_insn "lshrdi3_k"
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:SI 18))])]
""
- "{ if (GET_CODE (operands[2]) != CONST_INT
+ "{ if (GET_CODE (operands[2]) != CONST_INT
|| INTVAL (operands[2]) != 1) FAIL;} ")
(define_insn "ashrdi3_k"
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:SI 18))])]
""
- "{ if (GET_CODE (operands[2]) != CONST_INT
+ "{ if (GET_CODE (operands[2]) != CONST_INT
|| INTVAL (operands[2]) != 1) FAIL; } ")
-
\f
;; -------------------------------------------------------------------------
;; Unary arithmetic
(neg:SI (plus:SI (reg:SI 18)
(match_operand:SI 1 "arith_reg_operand" "r"))))
(set (reg:SI 18)
- (ne:SI (plus:SI (reg:SI 18) (match_dup 1))
+ (ne:SI (ior:SI (reg:SI 18) (match_dup 1))
(const_int 0)))]
""
"negc %1,%0"
""
"not %1,%0"
[(set_attr "type" "arith")])
-
\f
;; -------------------------------------------------------------------------
;; Zero extension instructions
(zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
""
"extu.b %1,%0"
- [(set_attr "type" "arith")])
+ [(set_attr "type" "arith")])
(define_insn "zero_extendqihi2"
[(set (match_operand:HI 0 "arith_reg_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
""
"extu.b %1,%0"
- [(set_attr "type" "arith")])
-
+ [(set_attr "type" "arith")])
\f
;; -------------------------------------------------------------------------
;; Sign extension instructions
(clobber (reg:SI 18))]
""
"mov %1,%S0\;mov %1,%R0\;shll %S0\;subc %S0,%S0"
- [(set_attr "length" "8")])
+ [(set_attr "length" "8")])
(define_insn "extendhisi2"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
exts.b %1,%0
mov.b %1,%0"
[(set_attr "type" "arith,load")])
-
\f
;; -------------------------------------------------------------------------
;; Move instructions
[(set_attr "type" "load,pload,load")
(set_attr "hit_stack" "yes")])
-(define_insn ""
- [(set (match_operand:SI 0 "push_operand" "=<,<")
- (match_operand:SI 1 "arith_reg_operand" "r,xl"))]
- ""
- "@
- mov.l %1,%0
- sts.l %1,%0"
- [(set_attr "type" "store")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "arith_reg_operand" "=r,xl")
- (match_operand:SI 1 "pop_operand" "=>,>"))]
- ""
- "@
- mov.l %1,%0
- lds.l %1,%0"
- [(set_attr "type" "load")])
-
(define_insn "clrt"
[(set (reg:SI 18) (const_int 0))]
""
"clrt")
-;(define_insn "movsi_pi"
-; [(set (match_operand:SI 0 "general_movdst_operand" "=r")
-; (mem:SI (post_inc (match_operand:SI 1 "register_operand" "r"))))]
-; ""
-; "mov.l @%1,%0\;add #4,%1"
-; [(set_attr "length" "4")])
-
-
(define_insn "movsi_i"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,r,<m,<,xl,xl,t,r")
- (match_operand:SI 1 "general_movsrc_operand" "Q,rI,>m,xl,t,r,xl,r,>,r,i"))]
+ [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,r,m,<,xl,xl,t,r")
+ (match_operand:SI 1 "general_movsrc_operand" "Q,rI,m,xl,t,r,xl,r,>,r,i"))]
""
"@
mov.l %1,%0
fake %1,%0"
[(set_attr "type" "pcload,move,load,move,store,store,move,load,move,move,move")
(set_attr "length" "*,*,*,*,*,*,*,*,*,8,*")])
-
+
(define_expand "movsi"
[(set (match_operand:SI 0 "general_movdst_operand" "")
(match_operand:SI 1 "general_movsrc_operand" ""))]
(define_insn "movqi_i"
- [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,>m,r,r,l")
- (match_operand:QI 1 "general_movsrc_operand" "ri,<m,r,t,l,r"))]
- "arith_reg_operand (operands[0], QImode)
+ [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
+ (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
+ "arith_reg_operand (operands[0], QImode)
|| arith_reg_operand (operands[1], QImode)"
"@
mov %1,%0
"if (prepare_move_operands(operands, QImode)) DONE; ")
(define_insn "movhi_i"
- [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,<m,r,l,r")
- (match_operand:HI 1 "general_movsrc_operand" "Q,rI,>m,t,r,l,r,i"))]
+ [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
+ (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
""
"@
mov.w %1,%0
""
"if (prepare_move_operands (operands, HImode)) DONE;")
-(define_insn ""
- [(set (match_operand:DI 0 "push_operand" "=<")
- (match_operand:DI 1 "arith_reg_operand" "r"))]
- ""
- "mov.l %T1,%0\;mov.l %01,%0"
- [(set_attr "length" "4")
- (set_attr "type" "store")])
-
(define_insn ""
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r")
(match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,i"))]
FAIL;
}")
-
+
(define_expand "movdi"
[(set (match_operand:DI 0 "general_movdst_operand" "")
(match_operand:DI 1 "general_movsrc_operand" ""))]
""
"if ( prepare_move_operands(operands, DImode)) DONE; ")
-(define_insn ""
- [(set (match_operand:DF 0 "push_operand" "=<")
- (match_operand:DF 1 "arith_reg_operand" "r"))]
- ""
- "mov.l %T1,%0\;mov.l %1,%0"
- [(set_attr "length" "4")
- (set_attr "type" "store")])
-
(define_insn "movdf_k"
[(set (match_operand:DF 0 "general_movdst_operand" "=r,r,m")
(match_operand:DF 1 "general_movsrc_operand" "r,m,r"))]
;; If the output is a register and the input is memory, we have to be careful
;; and see which word needs to be loaded first.
-;;
+
(define_split
[(set (match_operand:DF 0 "general_movdst_operand" "")
(match_operand:DF 1 "general_movsrc_operand" ""))]
""
"{ if (prepare_move_operands(operands, DFmode)) DONE; } ")
-(define_insn ""
- [(set (match_operand:SF 0 "push_operand" "=<")
- (match_operand:SF 1 "arith_reg_operand" "r"))]
- ""
- "mov.l %1,%0"
- [(set_attr "type" "store")])
-
-;; ??? Why do we have unsupported auto-inc in the dest, and auto-dec in the
-;; source? And why is the supported auto-dec dest and auto-inc source missing?
-
(define_insn "movsf_i"
- [(set (match_operand:SF 0 "general_movdst_operand" "=>,r,r,r,r,m,l,r")
- (match_operand:SF 1 "general_movsrc_operand" "r,<,r,I,m,r,r,l"))]
+ [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m,l,r")
+ (match_operand:SF 1 "general_movsrc_operand" "r,I,m,r,r,l"))]
""
"@
- mov.l %1,@%N0\;add #4,%N0
- add #-4,%1\;mov.l @%N1,%0
mov %1,%0
mov %1,%0
mov.l %1,%0
mov.l %1,%0
lds %1,%0
sts %1,%0"
- [(set_attr "type" "store,load,move,move,load,store,move,move")
- (set_attr "length" "4,4,*,*,*,*,*,*")])
+ [(set_attr "type" "move,move,load,store,move,move")])
(define_expand "movsf"
[(set (match_operand:SF 0 "general_movdst_operand" "")
(match_operand:SF 1 "general_movsrc_operand" ""))]
""
"if (prepare_move_operands (operands, SFmode)) DONE;")
-
\f
;; ------------------------------------------------------------------------
;; Define the real conditional branch instructions.
""
"* return output_branch (1, insn);"
[(set_attr "type" "cbranch")])
-
\f
;; Conditional branch insns
(label_ref (match_operand 0 "" ""))))]
""
"from_compare (operands, LEU);")
-
\f
;; ------------------------------------------------------------------------
;; Jump and linkage insns
"*
{
/* The length is 16 if the delay slot is unfilled. */
- if (get_attr_length(insn) >= 14)
+ if (get_attr_length(insn) >= 14)
{
return output_far_jump(insn, operands[0]);
}
(define_insn "dect"
[(parallel[
- (set (match_operand:SI 0 "register_operand" "=r")
+ (set (match_operand:SI 0 "arith_reg_operand" "=r")
(plus:SI (match_dup 0)
(const_int -1)))
(set (reg:SI 18)
;; This must use unspec, because this only works immediately before a casesi.
(define_insn "mova"
- [(set (reg:SI 0)
+ [(set (reg:SI 0)
(unspec [(label_ref (match_operand 0 "" ""))] 1))]
""
"mova %O0,r0"
}")
(define_insn "casesi_worker"
- [(set (reg:SI 0)
- (plus:SI (reg:SI 0)
+ [(set (reg:SI 0)
+ (plus:SI (reg:SI 0)
(mem:HI (plus:SI (reg:SI 0)
- (match_operand:SI 0 "register_operand" "=r")))))
+ (match_operand:SI 0 "arith_reg_operand" "=r")))))
(set (match_dup 0) (mem:HI (plus:SI (reg:SI 0)
(match_dup 0))))]
""
"*
- if (TARGET_BIGTABLE)
+ if (TARGET_BIGTABLE)
return \"mov.l @(r0,%0),%0\;add %0,r0\";
else
return \"mov.w @(r0,%0),%0\;add %0,r0\";"
""
""
[(set_attr "length" "0")])
-
\f
;; ------------------------------------------------------------------------
;; Scc instructions
;; Misc
;; -------------------------------------------------------------------------
-;; String/block move insn.
+;; String/block move insn.
(define_expand "movstrsi"
[(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
;; This matches cases where a stack pointer increment at the start of the
;; epilogue combines with a stack slot read loading the return value.
-(define_peephole
+(define_peephole
[(set (match_operand:SI 0 "arith_reg_operand" "")
(mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
;; See the comment on the dt combiner pattern above.
-(define_peephole
- [(set (match_operand:SI 0 "register_operand" "=r")
+(define_peephole
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
(plus:SI (match_dup 0)
(const_int -1)))
(set (reg:SI 18)
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