of that following instruction. **All prefixed instructions retain their
non-prefixed encoding and definition**.
-*Architectural Resource Allocation note: it is prohibited to accept RFCs
-which fundamentally violate this hard requirement. Under no circumstances
-must the Suffix space have an alternate instruction encoding allocated
-within SVP64 that is entirely different from the non-prefixed Defined
-Word. Hardware Implementors critically rely on this inviolate guarantee
-to implement High-Performance Multi-Issue micro-architectures that can
-sustain 100% throughput*
-
-| 0:5 | 6:31 | 32:63 |
-|--------|--------------|--------------|
-| EXT09 | v3.1 Prefix | v3.0/1 Suffix |
-
Two apparent exceptions to the above hard rule exist: SV Branch-Conditional
operations and LD/ST-update "Post-Increment" Mode. Post-Increment
was considered sufficiently high priority (significantly reducing hot-loop
is highly suited to High-Performance Computation (HPC), Supercomputing,
and parallel GPU Workloads.
+*Architectural Resource Allocation note: it is prohibited to accept RFCs
+which fundamentally violate this hard requirement. Under no circumstances
+must the Suffix space have an alternate instruction encoding allocated
+within SVP64 that is entirely different from the non-prefixed Defined
+Word. Hardware Implementors critically rely on this inviolate guarantee
+to implement High-Performance Multi-Issue micro-architectures that can
+sustain 100% throughput*
+
Subset implementations in hardware are permitted, as long as certain
rules are followed, allowing for full soft-emulation including future
revisions. Compliancy Subsets exist to ensure minimum levels of binary