if (info->indirect) {
if (program->uses_grid_size) {
for (unsigned i = 0; i < 3; ++i) {
- si_cp_copy_data(sctx,
+ si_cp_copy_data(sctx, sctx->gfx_cs,
COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
COPY_DATA_SRC_MEM, si_resource(info->indirect),
info->indirect_offset + 4 * i);
radeon_emit_array(cs, (const uint32_t*)data, size/4);
}
-void si_cp_copy_data(struct si_context *sctx,
+void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
unsigned src_sel, struct si_resource *src, unsigned src_offset)
{
- struct radeon_cmdbuf *cs = sctx->gfx_cs;
-
+ /* cs can point to the compute IB, which has the buffer list in gfx_cs. */
if (dst) {
- radeon_add_to_buffer_list(sctx, cs, dst,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dst,
RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
}
if (src) {
- radeon_add_to_buffer_list(sctx, cs, src,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, src,
RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
}
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
- si_cp_copy_data(sctx,
+ si_cp_copy_data(sctx, sctx->gfx_cs,
COPY_DATA_DST_MEM, buffer, va - buffer->gpu_address,
COPY_DATA_IMM, NULL, 1);
void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
unsigned offset, unsigned size, unsigned dst_sel,
unsigned engine, const void *data);
-void si_cp_copy_data(struct si_context *sctx,
+void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
unsigned src_sel, struct si_resource *src, unsigned src_offset);
radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
t->stride_in_dw);
- si_cp_copy_data(sctx,
+ si_cp_copy_data(sctx, sctx->gfx_cs,
COPY_DATA_REG, NULL,
R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
COPY_DATA_SRC_MEM, t->buf_filled_size,