add SV FP arithmetic in "Overflow" mode for FFT/DCT +/-

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
new file mode 100644 (file)
index 0000000..39e7190
--- /dev/null
+++ b/openpower/isa/svfparith.mdwn
@@ -0,0 +1,231 @@
+<!-- SVP64 FP Instructions here described are based on -->
+<!--  PowerISA Version 3.0 B Book 1 -->
+
+# Floating Add [Single]
+
+A-Form
+
+* faddso FRT,FRA,FRB (Rc=0)
+* faddso. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPADD32(FRA, FRB)
+    FRS <- FPSUB32(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Add [Double]
+
+A-Form
+
+* faddo FRT,FRA,FRB (Rc=0)
+* faddo. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPADD64(FRA, FRB)
+    FRS <- FPSUB64(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Subtract [Single]
+
+A-Form
+
+* fsubso FRT,FRA,FRB (Rc=0)
+* fsubso. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPSUB32(FRA, FRB)
+    FRS <- FPADD32(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Subtract [Double]
+
+A-Form
+
+* fsubo FRT,FRA,FRB (Rc=0)
+* fsubo. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPSUB64(FRA, FRB)
+    FRS <- FPADD64(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Multiply [Single]
+
+A-Form
+
+* fmulso FRT,FRA,FRC (Rc=0)
+* fmulso. FRT,FRA,FRC (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPMUL32(FRA, FRC)
+    FRS <- FPMUL32(FRA, FRC, -1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Multiply [Double]
+
+A-Form
+
+* fmulo FRT,FRA,FRC (Rc=0)
+* fmulo. FRT,FRA,FRC (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPMUL64(FRA, FRC)
+    FRS <- FPMUL64(FRA, FRC, -1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Divide [Single]
+
+A-Form
+
+* fdivso FRT,FRA,FRB (Rc=0)
+* fdivso. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPDIV32(FRA, FRB)
+    FRS <- FPDIV32(FRA, FRB, -1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Divide [Double]
+
+A-Form
+
+* fdivo FRT,FRA,FRB (Rc=0)
+* fdivo. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPDIV64(FRA, FRB)
+    FRS <- FPDIV64(FRA, FRB, -1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Multiply-Add [Single]
+
+A-Form
+
+* fmaddso FRT,FRA,FRC,FRB (Rc=0)
+* fmaddso. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
+    FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+
+# Floating Multiply-Sub [Single]
+
+A-Form
+
+* fmsubso FRT,FRA,FRC,FRB (Rc=0)
+* fmsubso. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
+    FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+
+# Floating Negative Multiply-Add [Single]
+
+A-Form
+
+* fnmaddso FRT,FRA,FRC,FRB (Rc=0)
+* fnmaddso. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+    FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+
+# Floating Negative Multiply-Sub [Single]
+
+A-Form
+
+* fnmsubso FRT,FRA,FRC,FRB (Rc=0)
+* fnmsubso. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+    FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+