+2007-09-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5080
+ * config/tc-i386.c (check_long_reg): Also handle cvttss2si.
+ (check_qword_reg): Also handle cvttsd2si.
+
2007-09-27 Kazu Hirata <kazu@codesourcery.com>
* config/m68k-parse.h (m68k_register): Use MBO instead of MBB.
|| i.tm.operand_types[op].bitfield.acc))
{
if (intel_syntax
- && i.tm.base_opcode == 0xf30f2d
+ && (i.tm.base_opcode == 0xf30f2d
+ || i.tm.base_opcode == 0xf30f2c)
&& !i.types[0].bitfield.regxmm)
{
- /* cvtss2si converts DWORD memory to Reg64. We want
- REX byte. */
+ /* cvtss2si/cvttss2si convert DWORD memory to Reg64. We
+ want REX byte. */
i.suffix = QWORD_MNEM_SUFFIX;
}
else
/* Prohibit these changes in the 64bit mode, since the
lowering is more complicated. */
if (intel_syntax
- && i.tm.base_opcode == 0xf20f2d
+ && (i.tm.base_opcode == 0xf20f2d
+ || i.tm.base_opcode == 0xf20f2c)
&& !i.types[0].bitfield.regxmm)
{
- /* cvtsd2si converts QWORD memory to Reg32. We don't want
- REX byte. */
+ /* cvtsd2si/cvttsd2si convert QWORD memory to Reg32. We
+ don't want REX byte. */
i.suffix = LONG_MNEM_SUFFIX;
}
else
+2007-09-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5080
+ * gas/i386/simd-intel.d: Updated.
+ * gas/i386/simd.d: Likewise.
+ * gas/i386/x86-64-simd-intel.d: Likewise.
+ * gas/i386/x86-64-simd.d: Likewise.
+
+ * gas/i386/simd.s: Add new tests for cvttsd2si and cvttss2si.
+ * gas/i386/x86-64-simd.s: Likewise.
+
2007-09-27 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/5072
[ ]*[a-f0-9]+: 0f 2a 00 cvtpi2ps xmm0,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: 0f 2d 00 cvtps2pi mm0,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si eax,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 5a 00 cvtsd2ss xmm0,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd xmm0,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[eax\]
+[ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si eax,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 5e 00 divsd xmm0,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: f3 0f 5e 00 divss xmm0,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 5f 00 maxsd xmm0,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq xmm0,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps xmm0,DWORD PTR \[eax\],0x0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[eax\]
+[ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si eax,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si eax,QWORD PTR \[eax\]
#pass
[ ]*[a-f0-9]+: 0f 2a 00 cvtpi2ps \(%eax\),%xmm0
[ ]*[a-f0-9]+: 0f 2d 00 cvtps2pi \(%eax\),%mm0
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%eax\),%eax
+[ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si \(%eax\),%eax
[ ]*[a-f0-9]+: f2 0f 5a 00 cvtsd2ss \(%eax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%eax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%eax\),%eax
+[ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si \(%eax\),%eax
[ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%eax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 5e 00 divss \(%eax\),%xmm0
[ ]*[a-f0-9]+: f2 0f 5f 00 maxsd \(%eax\),%xmm0
[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq \(%eax\),%xmm0
[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps \$0x0,\(%eax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%eax\),%eax
+[ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si \(%eax\),%eax
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%eax\),%eax
+[ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si \(%eax\),%eax
#pass
cvtpi2ps (%eax),%xmm0
cvtps2pi (%eax),%mm0
cvtsd2si (%eax),%eax
+ cvttsd2si (%eax),%eax
cvtsd2ss (%eax),%xmm0
cvtss2sd (%eax),%xmm0
cvtss2si (%eax),%eax
+ cvttss2si (%eax),%eax
divsd (%eax),%xmm0
divss (%eax),%xmm0
maxsd (%eax),%xmm0
.intel_syntax noprefix
cvtss2si eax,DWORD PTR [eax]
+ cvttss2si eax,DWORD PTR [eax]
cvtsd2si eax,QWORD PTR [eax]
+ cvttsd2si eax,QWORD PTR [eax]
[ ]*[a-f0-9]+: 0f 2d 00 cvtps2pi mm0,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si rax,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si eax,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2si rax,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 5a 00 cvtsd2ss xmm0,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd xmm0,DWORD PTR \[rax\]
-[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si rax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si rax,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si eax,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2si rax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 5e 00 divsd xmm0,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 0f 5e 00 divss xmm0,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 5f 00 maxsd xmm0,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps xmm0,DWORD PTR \[rax\],0x0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si rax,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si eax,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2si rax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si rax,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si eax,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2si rax,QWORD PTR \[rax\]
#pass
[ ]*[a-f0-9]+: 0f 2d 00 cvtps2pi \(%rax\),%mm0
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax
[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2siq \(%rax\),%rax
+[ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si \(%rax\),%eax
+[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2siq \(%rax\),%rax
[ ]*[a-f0-9]+: f2 0f 5a 00 cvtsd2ss \(%rax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
-[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax
+[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax
+[ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si \(%rax\),%eax
+[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2siq \(%rax\),%rax
[ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 5e 00 divss \(%rax\),%xmm0
[ ]*[a-f0-9]+: f2 0f 5f 00 maxsd \(%rax\),%xmm0
[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps \$0x0,\(%rax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax
[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax
+[ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si \(%rax\),%eax
+[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2siq \(%rax\),%rax
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax
[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2siq \(%rax\),%rax
+[ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si \(%rax\),%eax
+[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2siq \(%rax\),%rax
#pass
cvtps2pi (%rax),%mm0
cvtsd2si (%rax),%eax
cvtsd2siq (%rax),%rax
+ cvttsd2si (%rax),%eax
+ cvttsd2siq (%rax),%rax
cvtsd2ss (%rax),%xmm0
cvtss2sd (%rax),%xmm0
- cvtss2siq (%rax),%rax
cvtss2si (%rax),%eax
+ cvtss2siq (%rax),%rax
+ cvttss2si (%rax),%eax
+ cvttss2siq (%rax),%rax
divsd (%rax),%xmm0
divss (%rax),%xmm0
maxsd (%rax),%xmm0
.intel_syntax noprefix
cvtss2si eax,DWORD PTR [rax]
cvtss2si rax,DWORD PTR [rax]
+ cvttss2si eax,DWORD PTR [rax]
+ cvttss2si rax,DWORD PTR [rax]
cvtsd2si eax,QWORD PTR [rax]
cvtsd2si rax,QWORD PTR [rax]
+ cvttsd2si eax,QWORD PTR [rax]
+ cvttsd2si rax,QWORD PTR [rax]